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TLK110
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9.6.24 RMII Receive Timing
SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
Table 9-24. RMII Receive Timing
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
t₁
XI Clock Period
50 MHz Reference Clock
t₂
RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from XI rising
t₃
CRS ON delay
From JK symbol on PMD
Receive Pair to initial
assertion of CRS_DV
20
ns
10.8
17.6
t₄
CRS OFF delay
From TR symbol on PMD
Receive Pair to initial
assertion of CRS_DV
26.2
bits
t₅
RXD[1:0] and RX_ER latency
From symbol on Receive
Pair. * Elasticity buffer set
29.7
to default value (01)
t₆
RX_CLK Clock Period
50 MHz “Recovered clock”
while working in “RMII
receive clock” mode
t₇
RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from RX_CLK While working in “RMII
rising
receive clock” mode
20
ns
3.8
PMD
Input Pair
Idle
(J/K)
t₅
XI
RX_DV
t₂
t₃
Data
(TR)
t₄
Data
t₁
t₂
t₂
CRS_DV
t₂
RXD[1:0]
RX_ER
RX_CLK
t₇
t₆
t₇
t₇
Figure 9-24. RMII Receive Timing
NOTE
1. Per the RMII Specification, output delays assume a 25pF load.
2. CRS_DV is asserted asynchronously in order to minimize latency of control signals
through the PHY. CRS_DV may toggle synchronously at the end of the packet to indicate
CRS de-assertion.
3. RX_DV is synchronous to XI. While not part of the RMII specification, this signal is
provided to simplify recovery of receive data.
4. “RMII receive clock” mode is not part of the RMII specification that allows synchronization
of the MAC-PHY RX interface in RMII mode. Setting register 0x000A bit [0] is required to
activate this mode.
Copyright © 2011–2012, Texas Instruments Incorporated
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