TLK110 Datasheet, PDF (15/104 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK110
www.ti.com
SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
SW_STRAPN
Pin tied to Ground
PHY in Power Down
State
200 ms
Power up
or
Reset event Thrugh
HW_RESENT pin
Software Polls OUI Register
value (0x0002) to detect end
of PHY reset
Data = 2000
Data = FFFF
Software configures
SW_STRAP registers:
SWSCR1-3
(0x0009,0x000A,0x000B)
Software sets
Config_Done - bit [15] at
SWSCR1 Register (0x0009)
PHY starts power up
sequence using SW Strapping
configuration values
PHY in Operating mode
and tries to establish link
Figure 3-4. TLK110 SW Strap Programming
Figure 3-5 shows the timing relationship for typical SW Strapping programming.
SW_STRAPN
HW_RESETN
Config_Done
MDIO
Write/Read Transactions
200 ms
PHY State
Reset
Power Down
Wake up
Try to establish Link
Figure 3-5. TLK110 SW Strap Timing Diagram
Connecting an external pull-up resistor to pin 21 disables Software Strapping Mode during power up
and/or HW Reset.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLK110
Hardware Configuration
15