TLK110 Datasheet, PDF (61/104 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK110
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SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
8.1.12 Software Strap Control Register 3 (SWSCR3)
This register contains the configuration bits used as strapping options or virtual strapping pins during HW
RESET. These configuration values are programmed by the system processor after HW_RESET/POR,
and then the “Config Done” - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration. An
internal reset pulse is generated and the SW Strap bit values are latched into internal registers.
BIT BIT NAME
15:7 RESERVED
6 Polarity
Swap
5 MDI/MDIX
Swap
4 Bypass
4B/5B
3:0 Fast Link
Down Mode
Table 8-15. SW Strap Control register 3 (SWSCR3), address 0x000B
DEFAULT
0, RO
0, SWS, RW
DESCRIPTION
RESERVED: Writes ignored, read as 0.
Polarity Swap:
0, SWS, RW
1 = Inverted polarity on both pairs: TPTD+ ↔ TPTD-, TPRD+ ↔ TPRD-
0 = Normal polarity
Port Mirror function: To Enable port mirroring, set bit 5 and this bit high.
MDI/MDIX Swap:
0, SWS, RW
1 = Swap MDI pairs (Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal (Receive on TPRD pair, Transmit on TPTD pair)
Port Mirror function: To Enable port mirroring, set this bit and bit 6 high.
Bypass 4B/5B Encoder/Decoder Functionality:
0, SWS, RW
1 = Bypass the 4B/5B Encoder in TX path and the Decoder in RX path to allow direct 5-bit
TX and 5-bit RX interface to/from the MAC. In the TX path, the additional TXD [4] input
pin is the TDI (pin 12) and in the RX path, the additional RXD [4] output pin is the
RXERR (pin 41). Note: The PHY must be configured to operate in MII mode.
0 = Normal operation
Fast Link Down Modes:
Bit 3 Drop the link based on RX Error count of the MII interface – When a predefined number
of 32 RX Error occurrences in a 10µs interval is reached, the link will be dropped.
Bit 2 Drop the link based on MLT3 Errors count (Violation of the MLT3 coding in the DSP
output) – When a predefined number of 20 MLT3 Error occurrences in a 10µs interval is
reached, the link will be dropped.
Bit 1 Drop the link based on Low SNR Threshold – When a predefined number of 20
Threshold crossing occurrences in a 10µs interval is reached, the link will be dropped.
Bit 0 Drop the link based on Signal/Energy loss indication – When the Energy detector
indicates Energy Loss, the link will be dropped. Typical reaction time is 10µs.
The Fast Link Down function is an OR of all these 4 options, so the designer can enable
combinations of these conditions.
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