TLK110 Datasheet, PDF (7/104 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK110
www.ti.com
SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
2.7 JTAG Interface
PIN
NAME
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTN
TYPE
NO.
DESCRIPTION
8
I, PU JTAG Test Clock: This pin has a weak internal pullup.
12
I, PU JTAG Test Data Input: This pin has a weak internal pullup.
9
O JTAG Test Data Output
10
I, PU JTAG Test Mode Select: This pin has a weak internal pullup.
11
I, PU JTAG Reset: This pin is an active low asynchronous test reset. This pin has a weak internal pullup.
2.8 Reset and Power Down
PIN
NAME
NO.
TYPE
DESCRIPTION
RESETN
This pin is an active-low reset input that initializes or re-initializes all the internal registers of the
29
I, PU TLK110. Asserting this pin low for at least 1 µs will force a reset process to occur. All jumper
options are reinitialized as well. .
Register access is required for this pin to be configured either as power down or as an interrupt.
The default function of this pin is power down.
When this pin is configured for a power down function, an active low signal on this pin places the
PWR_DNN/INT
7
I, OD, PU device in power down mode.
When this pin is configured as an interrupt pin then this pin is asserted low when an interrupt
condition occurs. The pin has an open-drain output with a weak internal pull-up. Some
applications may require an external pull-up resistor.
2.9 Power and Bias Connections
PIN
NAME
RBIAS
PFBOUT
PFBIN1
PFBIN2
VDD33_IO
IOGND
DGND
AVDD33
AGND
RESERVED
TYPE
NO.
DESCRIPTION
24
I Bias Resistor Connection. Use a 4.87kΩ 1% resistor connected from RBIAS to GND.
23
O
Power Feedback Output. 10µf and 0.1μF capacitors (ceramic preferred), should be placed close to
PFBOUT.
In single-supply operation, connect this pin to PFBIN1 and PFBIN2 (pin 18 and pin 37). See Figure 3-1
for proper placement
In multiple supply operation, this pin is not used.
18
Power Feedback Input. These pins are fed with power from PFBOUT (pin 23) in single supply operation.
I ^{In multiple supply operation a 1.5V external power should be connected to these pins. A small capacitor}
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of 0.1µF should be connected close to each pin. The internal linear regulator is powered down by writing
to register 0x00d0.
32, 48 P I/O 3.3V Supply
35, 47 P I/O ground
36
P Digital ground
22
P Analog 3.3V power supply
15, 19 P Analog ground
20 I/O RESERVED: This pin must be pulled-up through 2.2 kΩ resistor to AVDD33 supply
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Pin Descriptions
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