TLK110 Datasheet, PDF (73/104 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK110
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SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
8.4.2 PHY Reset Control Register (PHYRCR)
This register provides ability to the system to reset or restart the PHY by register access.
Table 8-32. PHY Reset Control Register (PHYRCR), address 0x001F
BIT NAME
15 Software Reset
14 Software
Restart
13:0 RESERVED
DEFAULT
0, RW,SC
0, RW,SC
<00 0000 0000
0000>, RO
FUNCTION
Software Reset:
1 = Reset PHY. Allow the system to reset the PHY using register access. This bit is self cleared
and has same effect as Hardware reset pin.
0 = Normal Operation.
Software Restart:
1 = Reset PHY. Allow the system to restart the PHY using register access. This bit is self
cleared and resets all PHY circuitry except the registers.
0 = Normal Operation.
Writes ignored, read as 0.
8.4.3 TX_CLK Phase Shift Register (TXCPSR)
This register allows programming the phase of the MII transmit clock (TX_CLK pin). The TX_CLK has a
fixed phase to the XI pin. However the default phase, while fixed, may not be ideal for all systems,
therefore this register may be used by the system to align the reference clock (XI pin) to the TX_CLK. The
phase shift value is in 4ns units. The phase shift value should be between 0 and 10 (0ns to 40ns). If value
greater than 10 is written, the update value will be the written value modulo 10.
Table 8-33. TX_CLK Phase Shift Register (TXCPSR), address 0x0042
BIT NAME
DEFAULT
15:5 RESERVED <0000 0000
000>, RO
4 Phase Shift 0,RW,SC
Enable
3:0 Phase Shift <0000>,RW
Value
FUNCTION
RESERVED: Writes ignored, read as 0.
TX Clock Phase Shift Enable:
1 = Perform Phase Shift to the TX_CLK according to the value written to Phase Shift Value in bits
[4:0].
0 = No change in TX Clock phase
TX Clock Phase Shift Value:
The value of this register represents the current phase shift between Reference clock at XI and MII
Transmit Clock at TX_CLK. Any different value that will be written to these bits will shift TX_CLK by 4
times the difference (in nSec).
For example, if the value of this register was 0x2, Writing 0x9 to this register will shift TX_CLK by
28nS (4 times 7).However, since the maximum difference between XI and TX_CLK could be 40nSec
(value of 10) in case of writing value bigger than 10, the updated value will be the written value
modulo 10.
8.4.4 Voltage Regulator Control Register (VRCR)
This register gives the host processor the ability to power down the voltage-regulator block of the PHY via
register access. This power-down operation is available in systems operating with an external power
supply.
Table 8-34. Voltage Regulator Control Register (VRCR), address 0x00D0
BIT NAME
15 VRPD
DEFAULT
0, RW, SC
14:4 RESERVED <000 0000 0000>,
RW
3:0 VR Control <0000>, RW
FUNCTION
Voltage Regulator Power Down:
1 = Power Down. Allow the system to power down the voltage regulator block of the PHY
using register access.
0 = Normal Operation. Voltage Regulator is powered and outputs voltage on the PFBOUT
pin.
RESERVED: Must be written as 0.
Voltage Regulator Control This value should be ignored on read. To write to this register,
perform a read followed by a write with the desired value.
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