TLK110 Datasheet, PDF (67/104 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK110
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SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
Table 8-21. MII Interrupt Status Register 2 (MISR2), address 0x0013 (continued)
BIT
NAME
9 Polarity Changed INT
8 Jabber Detect INT
7 RESERVED
6 AN Error EN
5 Page Rec EN
4 Loopback FIFO OF/UF EN
3 MDI Crossover Changed EN
2 Sleep Mode Event EN
1 Polarity Changed EN
0 Jabber Detect EN
DEFAULT
0,RO, COR
0,RO
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
DESCRIPTION
Polarity Changed Interrupt:
1 = Data polarity changed interrupt pending.
0 = No Data polarity event pending.
Jabber Detect Event Interrupt:
1 = Jabber detect event interrupt pending.
0 = No Jabber detect event pending
RESERVED: Writes ignored, read as 0.
Enable Interrupt on Auto-Negotiation error event
Enable Interrupt on page receive event
Enable Interrupt on loopback FIFO overflow/underflow event
Enable Interrupt on change of MDI/X status
Enable Interrupt sleep mode event
Enable Interrupt on change of polarity status
Enable Interrupt on Jabber detection event
8.3.5 False Carrier Sense Counter Register (FCSCR)
This counter provides information required to implement the "False Carriers" attribute within the MAU
managed object class of Clause 30 of the IEEE 802.3u specification.
Table 8-22. False Carrier Sense Counter Register (FCSCR), address 0x0014
BIT NAME
15:8 RESERVED
7:0 FCSCNT
DEFAULT DESCRIPTION
<0000 0000>, RO RESERVED: Writes ignored, read as 0.
0,RO / COR
False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This counter stops when it
reaches its maximum count (FFh). When the counter exceeds half full (7Fh), an interrupt
event is generated. This register is cleared on read.
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