TLK110 Datasheet, PDF (22/104 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK110
SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
PHY
TX_EN
TXD[1:0]
RX_CLK
RX_DV
RX_ER
RXD[1:0]
CRS/RX_DV
TX_EN
TXD[1:0]
RX_CLK (optional)
RX_DV (optional)
RX_ER
RXD[1:0]
CRS/RX_DV
XI
MAC
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50Mhz
Clock Source
Figure 4-2. TLK110 RMII/MAC Connection
RMII function includes a programmable elastic buffer to adjust for the frequency differences between the
reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal
propagation delay based on expected maximum packet size and clock accuracy.
Table 4-1 indicates how to program the buffer FIFO based on the expected max packet size and clock
accuracy. It assumes that the RMII reference clock and the far-end transmitter clock have the same
accuracy.
Start Threshold RBR[1:0]
1(4-bits)
2(8-bits)
3(12-bits)
0(16-bits)
Table 4-1. Recommended RMII Packet Sizes
Latency Tolerance
2 bits
6 bits
10 bits
14 bits
Recommended packet size at
±50ppm
2400 bytes
7200 bytes
12000 bytes
16800 bytes
Recommended packet size at
±100ppm
1200 bytes
3600 bytes
6000 bytes
8400 bytes
22
Interfaces
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