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TLK110 Datasheet, PDF (74/104 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer
TLK110
SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
8.5 Cable Diagnostic Configuration/Result Registers
8.5.1 ALCD Registers Control and Results 1
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Table 8-35. ALCD Control and Results 1 Register, address 0x0155
BIT
BIT NAME
15 alcd_start
14:13
12 alcd_done
11:4 alcd_out1
3 RESERVED
2:0 alcd_ctrl
DEFAULT
<0>, SC
<00>, RO
<0>, RO
<0000
0000>, RO
<0>, RO
<000>,RW
DESCRIPTION
alcd_start:
RESERVED: Writes ignored, read as 0.
TPTD Diagnostic Bypass
1 = Bypass TPTD diagnostic. TDR on TPTD pair will not be executed.
0 = TDR is executed on TPTD pair
alcd_out1
RESERVED: Writes ignored, read as 0.
alcd_ctrl
<000>:
<001>:
<010>:
<011>:
<100>:
<101>:
<110>:
<111>:
8.5.2 Cable Diagnostic Specific Control Register (CDSCR)
This register is used to select the channel for which cable diagnostics test needs to be done. It has the
enable/bypass bits for the diagnostic tests and also allows defining the number of executed and averaged
TDR sequences.
Table 8-36. Cable Diagnostic Specific Control Register (CDSCR), address 0x0170
BIT
BIT NAME
15 RESERVED
14 Diagnostic Cross
Disable
13 Diagnostic TPTD
Bypass
12 Diagnostic TPRD
Bypass
11 RESERVED
10:8 Diagnostics Average
Cycles
7:0 RESERVED
DEFAULT
0,RO
0,RW
0,RW
0,RO
1,RW
<110>,RW
0,RO
DESCRIPTION
RESERVED: Writes ignored, read as 0.
Cross TDR Diagnostic mode
1 = Disable TDR Cross mode – TDR will be executed in regular mode only
0 = Diagnostic of crossing pairs is enabled In Cross Diagnostic mode, the TDR mechanism
is looking for reflection on the other pair to check short between pairs.
TPTD Diagnostic Bypass
1 = Bypass TPTD diagnostic. TDR on TPTD pair will not be executed.
0 = TDR is executed on TPTD pair
In bypass TPTD, results are available in TPRD slots.
TPRD Diagnostic Bypass
1 = Bypass TPRD diagnostic. TDR on TPRD pair will not be executed.
0 = TDR is executed on TPRD pair
RESERVED: Must be Set to 1.
Number Of TDR Cycles to Average:
<000>: 1 TDR cycle
<001>: 2 TDR cycles
<010>: 4 TDR cycles
<011>: 8 TDR cycles
<100>: 16 TDR cycles
<101>: 32 TDR cycles
<110>: 64 TDR cycles (default)
<111>: Reserved
RESERVED: Writes ignored, read as 0.
74
Register Block
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