TLK110 Datasheet, PDF (14/104 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK110
SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
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3.7 PHY Address
The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown in Table 3-2.
Table 3-2. PHY Address Mapping
PIN #
42
43
44
45
46
PHYAD FUNCTION
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4
RXD FUNCTION
COL
RXD_0
RXD_1
RXD_2
RXD_3
Each TLK110 or port sharing an MDIO bus in a system must have a unique physical address. With 5
address input pins, the TLK110 can support PHY Address values 0 (<00000>) through 31 (<11111>). The
address-pin states are latched into an internal register at device power-up and hardware reset. Because
all the PHYAD[4:0] pins have weak internal pull-down/up resistors, the default setting for the PHY address
is 00001 (0x01h).
See Figure 3-3 for an example of a PHYAD connection to external components. In this example, the
PHYAD configuration results in address 00011 (0x03h).
PHYAD4 = 0 PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1
2.2 kW
VCC
Figure 3-3. PHYAD Configuration Example
3.8 Software Strapping Mode
The TLK110 provides a mechanism to extend the number of configuration pins to allow wider system
programmability of PHY functions.
Connecting an external pull-down to pin 21 causes the device to enter SW Strapping Mode after power-up
or a hardware reset event. In this mode the device wakes up after power-up/hardware reset in power
down mode. While in power down (in SW strap mode only) the PHY allows the system processor to
access the dedicated Strapping Registers and configure modes of operation. Once the dedicated
Strapping Registers are programmed, setting the SW Strapping Mode Release register bit (“Configuration
done”), bit 15 of register SWSCR1(0x0009), must be done in order to take the device out of power-down
mode. An internal reset pulse is generated and the SW Strap Register values are latched into internal
registers. Unless a new Power-up/HW reset was applied, the configured SW Strap Register values will
function as default values. Generation of Software Reset/Software Restart - bits 15/14 of register
PHYRCR (0x001F) will not clear the configured SW Strap bit values.
There are 3 Software Strapping control registers: SWSCR1 (0x0009), SWSCR2 (0x000A) and
SWSCR3(0x000B) contain the configuration bits used as strapping options or virtual strapping pins during
HW Reset or Power-Up.
The TLK110 Software Strap mechanism behavior is shown in Figure 3-4.
14
Hardware Configuration
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