TLK110 Datasheet, PDF (70/104 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK110
SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
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8.3.9 LED Control Register (LEDCR)
This register provides the ability to directly manually control any or all LED outputs.
Table 8-26. LED Control Register (LEDCR), address 0x0018
BIT NAME
15:11 RESERVED
10:9 Blink Rate
8 LED Speed Polarity
7 LED Link Polarity
6 LED Active Polarity
5 Drive Speed LED
4 Drive Link LED
3 Drive Active LED
2 Speed LED On/Off Setting
1 Link LED On/Off Setting
0 Act LED On/Off Setting
DEFAULT
<0000 0>, ro
<10>,RW
1,RW, Strap
1,RW, Strap
1,RW, Strap
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
DESCRIPTION
RESERVED: Writes ignored, read as 0.
LED Blinking Rate (ON/OFF duration):
00 = 20 Hz (50mSec)
01 = 10 Hz (100mSec)
10 = 5 Hz(200mSec)
11 = 2 Hz(500mSec)
LED Speed Polarity Setting:
1 = Active High polarity setting.
0 = Active Low polarity setting.
Speed LED’s polarity defined by strapping value of this pin. This register allows
override of this strapping value.
LED Link Polarity Setting:
1 = Active High polarity setting.
0 = Active Low polarity setting.
Link LED’s polarity defined by strapping value of this pin. This register allows
override of this strapping value.
LED Activity Polarity Setting:
1 = Active High polarity setting.
0 = Active Low polarity setting.
Activity LED’s polarity defined by strapping value of this pin. This register allows
override of this strapping value.
Drive LED Speed to the forced On/Off setting defied in bit 2:
1 = Drive value of On/Off bit onto LED_SPEED output pin.
0 = Normal operation.
Drive LED Link to the forced On/Off setting defied in bit 1:
1 = Drive value of On/Off bit onto LED_LINK output pin.
0 = Normal operation.
Drive LED Activity to the forced On/Off setting defied in bit 0:
1 = Drive value of On/Off bit onto LED_ACT output pin.
0 = Normal operation.
Value to force on Speed LED output
Value to force on Link LED output
Value to force on Activity LED output
8.3.10 PHY Control Register (PHYCR)
This register provides the ability to control and set general functionality inside the PHY.
Table 8-27. PHY Control Register (PHYCR), address 0x0019
BIT NAME
15 Auto MDI/X
Enable
DEFAULT
1,RW,Strap
14 Force MDI/X 0,RW
13 Pause RX
Status
0,RO
12 Pause TX
Status
0,RO
DESCRIPTION
Auto-MDIX Enable:
1 = Enable Auto-negotiation Auto-MDIX capability.
0 = Disable Auto- negotiation Auto-MDIX capability.
Force MDIX:
1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair)
0 = Normal operation. (Transmit on TPTD pair, Receive on TPRD pair)
Pause Receive Negotiated Status: Indicates that pause receive should be enabled in the MAC.
Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause
Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.
Pause Transmit Negotiated Status:
Indicates that pause transmit should be enabled in the MAC. Based on bits [11:10] in ANAR register
and bits [11:10] in ANLPAR register settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause
Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.
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