TLK110 Datasheet, PDF (18/104 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK110
SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012
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3.10.2 Far-End Loopback
Far-end (Reverse) loopback is a special test mode to allow testing the PHY from the link-partner side. In
this mode, data that is received from the link partner passes through the PHY's receiver, looped back on
the MII and transmitted back to the link partner. Figure 3-8 shows Far-end loopback functionality.
MAC/
Switch
M
I
PCS
I
Signal
Process
PHY Digital
PHY
AFE
XFMR _{CAT5 Cable}
&
Link Partner
RJ45
Reverse Loopback
Figure 3-8. Block Diagram, Far-End Loopback Mode
The Reverse Loopback mode is selected by setting bit 4 in the BIST Control Register (BISCR), MII
register address 0x0016.
While in Reverse Loopback mode the data is looped back and also transmitted onto the MAC Interface
and all data signals that come from the MAC are ignored.
3.11 BIST
The TLK110 incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit
testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data
paths. The BIST can be performed using both internal loopback (digital or analog) or external loop back
using a cable fixture. The BIST simulates pseudo-random data transfer scenarios in format of real packets
and IPG on the lines. The BIST allows full control of the packet lengths and of the Inter-Packet Gap (IPG).
The BIST is implemented with independent transmit and receive paths, with the transmit block generating
a continuous stream of a pseudo-random sequence. The TLK110 generates a 15-bit pseudo-random
sequence for the BIST. The received data is compared to the generated pseudo-random data by the BIST
Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The number of error bytes
that the PRBS checker received is stored in the BICSR1 register (0x001Bh). The status of whether the
PRBS checker is locked to the incoming receive bit stream, whether the PRBS has lost sync, and whether
the packet generator is busy, can be read from the BISCR register (0x0016h).
The PRBS test can be put in a continuous mode or single mode by using bit 14 of the BISCR register
(0x0016h). In continuous mode, when one of the PRBS counters reaches the maximum value, the counter
starts counting from zero again. In single mode, when the PRBS counter reaches its maximum value, the
PRBS checker stops counting.
TLK110 allows the user to control the length of the PRBS packet. By programming the BICSR2 register
(0x001Ch) one can set the length of the PRBS packet. There is also an option to generate a single-packet
transmission of two types, 64 and 1518 bytes, through register bit 13 of the BISCR register (0x0016h).
The single generated packet is composed of a constant data.
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