LM3S5C36 Datasheet, PDF (957/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Stellaris^® LM3S5C36 Microcontroller
Figure 20-1. QEI Block Diagram
Control & Status
QEICTL
QEISTAT
QEILOAD
Velocity Timer
QEITIME
PhA
PhB
IDX
Velocity
Predivider
clk
Quadrature
Encoder dir
Velocity Accumulator
QEICOUNT
QEISPEED
QEIMAXPOS
Position Integrator
QEIPOS
QEIINTEN
Interrupt Control
QEIRIS
QEIISC
Interrupt
20.2
Signal Description
The following table lists the external signals of the QEI module and describes the function of each.
The QEI signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin
placements for these QEI signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 432) should be set to choose the QEI function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 449) to assign the QEI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 412.
Table 20-1. QEI Signals (64LQFP)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
IDX0
47
PB2 (2)
I
56
PB6 (5)
58
PB4 (6)
61
PD0 (3)
TTL
QEI module 0 index.
PhA0
2
PE2 (4)
I
11
PC4 (2)
62
PD1 (3)
TTL
QEI module 0 phase A.
PhB0
1
PE3 (4)
I
15
PC6 (2)
16
PC7 (2)
TTL
QEI module 0 phase B.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
January 23, 2012
957
Texas Instruments-Production Data