LM3S5C36 Datasheet, PDF (851/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Stellaris^® LM3S5C36 Microcontroller
Register 98: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1),
offset 0x116
Register 99: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2),
offset 0x126
Register 100: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3),
offset 0x136
Register 101: USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4),
offset 0x146
Register 102: USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5),
offset 0x156
Register 103: USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6),
offset 0x166
Register 104: USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7),
offset 0x176
Register 105: USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8),
offset 0x186
Register 106: USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9),
offset 0x196
Register 107: USB Receive Control and Status Endpoint 10 Low
(USBRXCSRL10), offset 0x1A6
Register 108: USB Receive Control and Status Endpoint 11 Low
(USBRXCSRL11), offset 0x1B6
Register 109: USB Receive Control and Status Endpoint 12 Low
(USBRXCSRL12), offset 0x1C6
Register 110: USB Receive Control and Status Endpoint 13 Low
(USBRXCSRL13), offset 0x1D6
Register 111: USB Receive Control and Status Endpoint 14 Low
(USBRXCSRL14), offset 0x1E6
Register 112: USB Receive Control and Status Endpoint 15 Low
(USBRXCSRL15), offset 0x1F6
USBRXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected receive endpoint.
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1)
Base 0x4005.0000
Offset 0x116
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
CLRDT STALLED STALL FLUSH DATAERR OVER FULL RXRDY
Type W1C
R/W
R/W
R/W
RO
R/W
RO
R/W
Reset
0
0
0
0
0
0
0
0
January 23, 2012
851
Texas Instruments-Production Data