LM3S5C36 Datasheet, PDF (5/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Stellaris^® LM3S5C36 Microcontroller
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Hibernation Module .............................................................................................. 280
6.1 Block Diagram ............................................................................................................ 281
6.2 Signal Description ....................................................................................................... 281
6.3 Functional Description ................................................................................................. 282
6.3.1 Register Access Timing ............................................................................................... 282
6.3.2 Hibernation Clock Source ............................................................................................ 282
6.3.3 System Implementation ............................................................................................... 284
6.3.4 Battery Management ................................................................................................... 284
6.3.5 Real-Time Clock .......................................................................................................... 285
6.3.6 Battery-Backed Memory .............................................................................................. 285
6.3.7 Power Control Using HIB ............................................................................................. 285
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 286
6.3.9 Initiating Hibernate ...................................................................................................... 286
6.3.10 Waking from Hibernate ................................................................................................ 286
6.3.11 Interrupts and Status ................................................................................................... 286
6.4 Initialization and Configuration ..................................................................................... 287
6.4.1 Initialization ................................................................................................................. 287
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 288
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 288
6.4.4 External Wake-Up from Hibernation .............................................................................. 288
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 288
6.5 Register Map .............................................................................................................. 289
6.6 Register Descriptions .................................................................................................. 289
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7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 306
Block Diagram ............................................................................................................ 306
Functional Description ................................................................................................. 306
SRAM ........................................................................................................................ 307
ROM .......................................................................................................................... 307
Flash Memory ............................................................................................................. 309
Register Map .............................................................................................................. 314
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 316
Memory Register Descriptions (System Control Offset) .................................................. 328
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Micro Direct Memory Access (μDMA) ................................................................ 352
8.1 Block Diagram ............................................................................................................ 353
8.2 Functional Description ................................................................................................. 353
8.2.1 Channel Assignments .................................................................................................. 354
8.2.2 Priority ........................................................................................................................ 355
8.2.3 Arbitration Size ............................................................................................................ 355
8.2.4 Request Types ............................................................................................................ 356
8.2.5 Channel Configuration ................................................................................................. 356
8.2.6 Transfer Modes ........................................................................................................... 358
8.2.7 Transfer Size and Increment ........................................................................................ 366
8.2.8 Peripheral Interface ..................................................................................................... 366
8.2.9 Software Request ........................................................................................................ 366
8.2.10 Interrupts and Errors .................................................................................................... 367
8.3 Initialization and Configuration ..................................................................................... 367
8.3.1 Module Initialization ..................................................................................................... 367
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 368
January 23, 2012
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