LM3S5C36 Datasheet, PDF (887/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Stellaris^® LM3S5C36 Microcontroller
19.3.6
within the pwmA or pwmB signal. Note that interrupts and ADC triggers are based on the raw events;
delays in the PWM signal edges caused by the dead-band generator are not taken into account.
Synchronization Methods
The PWM module provides four PWM generators, each providing two PWM outputs that may be
used in a wide variety of applications. Generally speaking, the PWM is used in one of two categories
of operation:
■ Unsynchronized. The PWM generator and its two output signals are used alone, independent
of other PWM generators.
■ Synchronized. The PWM generator and its two outputs signals are used in conjunction with
other PWM generators using a common, unified time base. If multiple PWM generators are
configured with the same counter load value, synchronization can be used to guarantee that
they also have the same count value (the PWM generators must be configured before they are
synchronized). With this feature, more than two PWMn signals can be produced with a known
relationship between the edges of those signals because the counters always have the same
values. Other states in the module provide mechanisms to maintain the common time base and
mutual synchronization.
The counter in a PWM generator can be reset to zero by writing the PWM Time Base Sync
(PWMSYNC) register and setting the SYNCn bit associated with the generator. Multiple PWM
generators can be synchronized together by setting all necessary SYNCn bits in one access. For
example, setting the SYNC0 and SYNC1 bits in the PWMSYNC register causes the counters in PWM
generators 0 and 1 to reset together.
Additional synchronization can occur between multiple PWM generators by updating register contents
in one of the following three ways:
■ Immediately. The write value has immediate effect, and the hardware reacts immediately.
■ Locally Synchronized. The write value does not affect the logic until the counter reaches the
value zero at the end of the PWM cycle. In this case, the effect of the write is deferred, providing
a guaranteed defined behavior and preventing overly short or overly long output PWM pulses.
■ Globally Synchronized. The write value does not affect the logic until two sequential events
have occurred: (1) the Update mode for the generator function is programmed for global
synchronization in the PWMnCTL register, and (2) the counter reaches zero at the end of the
PWM cycle. In this case, the effect of the write is deferred until the end of the PWM cycle following
the end of all updates. This mode allows multiple items in multiple PWM generators to be updated
simultaneously without odd effects during the update; everything runs from the old values until
a point at which they all run from the new values. The Update mode of the load and comparator
match values can be individually configured in each PWM generator block. It typically makes
sense to use the synchronous update mechanism across PWM generator blocks when the timers
in those blocks are synchronized, although this is not required in order for this mechanism to
function properly.
The following registers provide either local or global synchronization based on the state of various
Update mode bits and fields in the PWMnCTL register (LOADUPD; CMPAUPD; CMPBUPD):
■ Generator Registers: PWMnLOAD, PWMnCMPA, and PWMnCMPB
The following registers default to immediate update, but are provided with the optional functionality
of synchronously updating rather than having all updates take immediate effect:
January 23, 2012
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