LM3S5C36 Datasheet, PDF (58/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Architectural Overview
1.3.8
1.4
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port
(SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one
module providing all the normal JTAG debug and test functionality plus real-time access to system
memory without halting the core or requiring any target resident code. The SWJ-DP interface has
the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
Packaging and Temperature
■ Industrial-range (-40°C to 85°C) 64-pin RoHS-compliant LQFP package
Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 978
■ “Signal Tables” on page 979
■ “Operating Characteristics” on page 1002
■ “Electrical Characteristics” on page 1003
■ “Package Information” on page 1063
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January 23, 2012
Texas Instruments-Production Data