LM3S5C36 Datasheet, PDF (539/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Stellaris^® LM3S5C36 Microcontroller
The arbitration size of the μDMA transfer must be a power of 2, and the associated IE bits in the
ADDSSCTLn register must be set. For example, if the μDMA channel of SS0 has an arbitration
size of four, the IE3 bit (4th sample) and the IE7 bit (8th sample) must be set. Thus the μDMA
request occurs every time 4 samples have been acquired. No other special steps are needed to
enable the ADC module for μDMA operation.
Refer to the “Micro Direct Memory Access (μDMA)” on page 352 for more details about programming
the μDMA controller.
12.3.2.3
Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample
sequencer units with the same priority do not provide consistent results, so software must ensure
that all active sample sequencer units have a unique priority value.
12.3.2.4
Sampling Events
Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. Trigger sources include processor (default), analog comparators, an external
signal on GPIO PB4, a GP Timer, a PWM generator, and continuous sampling. The processor
triggers sampling by setting the SSx bits in the ADC Processor Sample Sequence Initiate
(ADCPSSI) register.
Care must be taken when using the continuous sampling trigger. If a sequencer's priority is too high,
it is possible to starve other lower priority sequencers. Generally, a sample sequencer using
continuous sampling should be set to the lowest priority. Continuous sampling can be used with a
digital comparator to cause an interrupt when a particular voltage is seen on an input.
12.3.2.5
Sample Phase Control
The trigger source for ADC0 and ADC1 may be independent or the two ADC modules may operate
from the same trigger source and operate on the same or different inputs. If the converters are
running at the same sample rate, they may be configured to start the conversions coincidentally or
with one of 15 different discrete phases relative to each other. The sample time can be delayed
from the standard sampling time in 22.5° increments up to 337.5º using the ADC Sample Phase
Control (ADCSPC) register. Figure 12-3 on page 539 shows an example of various phase
relationships at a 1 Msps rate.
Figure 12-3. ADC Sample Phases
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ADC Sample Clock
PHASE 0x0 (0.0°)
PHASE 0x1 (22.5°)
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.
.
.
.
.
PHASE 0xE (315.0°)
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PHASE 0xF (337.5°)
This feature can be used to double the sampling rate of an input. Both ADC module 0 and ADC
module 1 can be programmed to sample the same input. ADC module 0 could sample at the standard
January 23, 2012
539
Texas Instruments-Production Data