LM3S5C36 Datasheet, PDF (14/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Revision History .................................................................................................. 33
Documentation Conventions ................................................................................ 37
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 64
Processor Register Map ....................................................................................... 65
PSR Register Combinations ................................................................................. 70
Memory Map ....................................................................................................... 78
Memory Access Behavior ..................................................................................... 81
SRAM Memory Bit-Banding Regions .................................................................... 83
Peripheral Memory Bit-Banding Regions ............................................................... 83
Exception Types .................................................................................................. 89
Interrupts ............................................................................................................ 89
Exception Return Behavior ................................................................................... 94
Faults ................................................................................................................. 95
Fault Status and Fault Address Registers .............................................................. 96
Cortex-M3 Instruction Summary ........................................................................... 98
Core Peripheral Register Regions ....................................................................... 101
Memory Attributes Summary .............................................................................. 104
TEX, S, C, and B Bit Field Encoding ................................................................... 107
Cache Policy for Memory Attribute Encoding ....................................................... 108
AP Bit Field Encoding ........................................................................................ 108
Memory Region Attributes for Stellaris Microcontrollers ........................................ 108
Peripherals Register Map ................................................................................... 109
Interrupt Priority Levels ...................................................................................... 136
Example SIZE Field Values ................................................................................ 164
JTAG_SWD_SWO Signals (64LQFP) ................................................................. 168
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 169
JTAG Instruction Register Commands ................................................................. 175
System Control & Clocks Signals (64LQFP) ........................................................ 179
Reset Sources ................................................................................................... 180
Clock Source Options ........................................................................................ 187
Possible System Clock Frequencies Using the SYSDIV Field ............................... 190
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 190
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 191
System Control Register Map ............................................................................. 196
RCC2 Fields that Override RCC Fields ............................................................... 217
Hibernate Signals (64LQFP) ............................................................................... 281
Hibernation Module Clock Operation ................................................................... 287
Hibernation Module Register Map ....................................................................... 289
Flash Memory Protection Policy Combinations .................................................... 310
User-Programmable Flash Memory Resident Registers ....................................... 314
Flash Register Map ............................................................................................ 315
μDMA Channel Assignments .............................................................................. 354
Request Type Support ....................................................................................... 356
Control Structure Memory Map ........................................................................... 357
Channel Control Structure .................................................................................. 357
μDMA Read Example: 8-Bit Peripheral ................................................................ 366
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January 23, 2012
Texas Instruments-Production Data