LM3S5C36 Datasheet, PDF (844/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Universal Serial Bus (USB) Controller
Bit/Field
7
6
5
4
3
2
1
Name
reserved
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register.
Endpoint Stalled
Value Description
0 A STALL handshake has not been transmitted.
1 A STALL handshake has been transmitted. The FIFO is flushed
and the TXRDY bit is cleared.
Software must clear this bit.
Send STALL
Value Description
0 No effect.
1 Issues a STALL handshake to an IN token.
Software clears this bit to terminate the STALL condition.
Note: This bit has no effect in isochronous transfers.
Flush FIFO
Value Description
0 No effect.
1 Flushes the latest packet from the endpoint transmit FIFO. The
FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit
in the USBTXIS register is also set in this situation.
This bit may be set simultaneously with the TXRDY bit to abort the packet
that is currently being loaded into the FIFO. Note that if the FIFO is
double-buffered, FLUSH may have to be set twice to completely clear
the FIFO.
Important: ^{This bit should only be set when the TXRDY bit is set. At}
other times, it may cause data to be corrupted.
0
Underrun
Value Description
0 No underrun.
1 An IN token has been received when TXRDY is not set.
Software must clear this bit.
0
FIFO Not Empty
Value Description
0 The FIFO is empty.
1 At least one packet is in the transmit FIFO.
844
January 23, 2012
Texas Instruments-Production Data