LM3S5C36 Datasheet, PDF (11/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Stellaris^® LM3S5C36 Microcontroller
List of Figures
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Stellaris LM3S5C36 Microcontroller High-Level Block Diagram ............................... 40
CPU Block Diagram ............................................................................................. 61
TPIU Block Diagram ............................................................................................ 62
Cortex-M3 Register Set ........................................................................................ 64
Bit-Band Mapping ................................................................................................ 84
Data Storage ....................................................................................................... 85
Vector Table ........................................................................................................ 91
Exception Stack Frame ........................................................................................ 93
SRD Use Example ............................................................................................. 107
JTAG Module Block Diagram .............................................................................. 168
Test Access Port State Machine ......................................................................... 171
IDCODE Register Format ................................................................................... 177
BYPASS Register Format ................................................................................... 177
Boundary Scan Register Format ......................................................................... 178
Basic RST Configuration .................................................................................... 182
External Circuitry to Extend Power-On Reset ....................................................... 182
Reset Circuit Controlled by Switch ...................................................................... 183
Power Architecture ............................................................................................ 186
Main Clock Tree ................................................................................................ 189
Hibernation Module Block Diagram ..................................................................... 281
Using a Crystal as the Hibernation Clock Source ................................................. 283
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 284
Internal Memory Block Diagram .......................................................................... 306
μDMA Block Diagram ......................................................................................... 353
Example of Ping-Pong μDMA Transaction ........................................................... 359
Memory Scatter-Gather, Setup and Configuration ................................................ 361
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 362
Peripheral Scatter-Gather, Setup and Configuration ............................................. 364
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 365
Digital I/O Pads ................................................................................................. 415
Analog/Digital I/O Pads ...................................................................................... 416
GPIODATA Write Example ................................................................................. 417
GPIODATA Read Example ................................................................................. 417
GPTM Module Block Diagram ............................................................................ 464
Timer Daisy Chain ............................................................................................. 468
Input Edge-Count Mode Example ....................................................................... 470
16-Bit Input Edge-Time Mode Example ............................................................... 471
16-Bit PWM Mode Example ................................................................................ 473
WDT Module Block Diagram .............................................................................. 510
Implementation of Two ADC Blocks .................................................................... 535
ADC Module Block Diagram ............................................................................... 536
ADC Sample Phases ......................................................................................... 539
Doubling the ADC Sample Rate .......................................................................... 540
Skewed Sampling .............................................................................................. 540
Sample Averaging Example ............................................................................... 541
January 23, 2012
11
Texas Instruments-Production Data