LM3S5C36 Datasheet, PDF (7/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Stellaris^® LM3S5C36 Microcontroller
12.3.3 Hardware Sample Averaging Circuit ............................................................................. 541
12.3.4 Analog-to-Digital Converter .......................................................................................... 541
12.3.5 Differential Sampling ................................................................................................... 545
12.3.6 Internal Temperature Sensor ........................................................................................ 547
12.3.7 Digital Comparator Unit ............................................................................................... 548
12.4 Initialization and Configuration ..................................................................................... 552
12.4.1 Module Initialization ..................................................................................................... 552
12.4.2 Sample Sequencer Configuration ................................................................................. 553
12.5 Register Map .............................................................................................................. 553
12.6 Register Descriptions .................................................................................................. 555
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 614
13.1 Block Diagram ............................................................................................................ 615
13.2 Signal Description ....................................................................................................... 615
13.3 Functional Description ................................................................................................. 616
13.3.1 Transmit/Receive Logic ............................................................................................... 616
13.3.2 Baud-Rate Generation ................................................................................................. 617
13.3.3 Data Transmission ...................................................................................................... 617
13.3.4 Serial IR (SIR) ............................................................................................................. 618
13.3.5 ISO 7816 Support ....................................................................................................... 619
13.3.6 LIN Support ................................................................................................................ 619
13.3.7 FIFO Operation ........................................................................................................... 621
13.3.8 Interrupts .................................................................................................................... 621
13.3.9 Loopback Operation .................................................................................................... 622
13.3.10 DMA Operation ........................................................................................................... 622
13.4 Initialization and Configuration ..................................................................................... 623
13.5 Register Map .............................................................................................................. 624
13.6 Register Descriptions .................................................................................................. 625
14 Synchronous Serial Interface (SSI) .................................................................... 670
14.1 Block Diagram ............................................................................................................ 671
14.2 Signal Description ....................................................................................................... 671
14.3 Functional Description ................................................................................................. 672
14.3.1 Bit Rate Generation ..................................................................................................... 672
14.3.2 FIFO Operation ........................................................................................................... 672
14.3.3 Interrupts .................................................................................................................... 673
14.3.4 Frame Formats ........................................................................................................... 674
14.3.5 DMA Operation ........................................................................................................... 681
14.4 Initialization and Configuration ..................................................................................... 682
14.5 Register Map .............................................................................................................. 683
14.6 Register Descriptions .................................................................................................. 684
15 Inter-Integrated Circuit (I²C) Interface ................................................................ 712
15.1 Block Diagram ............................................................................................................ 713
15.2 Signal Description ....................................................................................................... 713
15.3 Functional Description ................................................................................................. 713
15.3.1 I²C Bus Functional Overview ........................................................................................ 714
15.3.2 Available Speed Modes ............................................................................................... 716
15.3.3 Interrupts .................................................................................................................... 717
15.3.4 Loopback Operation .................................................................................................... 718
15.3.5 Command Sequence Flow Charts ................................................................................ 718
January 23, 2012
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