LM3S5C36 Datasheet, PDF (20/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Table of Contents
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
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Register 26:
Register 27:
Register 28:
Register 29:
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Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 228
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 229
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 231
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 233
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 236
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 238
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 240
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 241
Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 245
Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 247
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 249
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 250
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 253
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 256
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 258
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 261
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 264
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 267
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 269
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 271
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 273
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 275
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 278
Hibernation Module ..................................................................................................................... 280
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 290
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 291
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 292
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 293
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 294
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 297
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 299
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 301
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 303
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 304
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 305
Internal Memory ........................................................................................................................... 306
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 317
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 318
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 319
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 322
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 323
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 324
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 325
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 326
Register 9: Flash Control (FCTL), offset 0x0F8 ................................................................................. 327
Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 328
Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 329
Register 12: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 330
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January 23, 2012
Texas Instruments-Production Data