LM3S5C36 Datasheet, PDF (25/1068 Pages) Texas Instruments – Stellaris® LM3S5C36 Microcontroller

Stellaris^® LM3S5C36 Microcontroller
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Register 29:
UART Control (UARTCTL), offset 0x030 ......................................................................... 638
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 641
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 643
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 646
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 649
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 652
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 654
UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 655
UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 656
UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 657
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 658
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 659
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 660
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 661
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 662
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 663
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 664
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 665
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 666
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 667
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 668
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 669
Synchronous Serial Interface (SSI) ............................................................................................ 670
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 685
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 687
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 689
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 690
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 692
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 693
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 694
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 696
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 698
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 699
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 700
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 701
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 702
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 703
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 704
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 705
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 706
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 707
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 708
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 709
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 710
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 711
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 712
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 728
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 729
January 23, 2012
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