LMK00306_16 Datasheet, PDF (9/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
Electrical Characteristics (continued)
Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ T_A ≤ 85 °C, CLKin driven
differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A
= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. ⁽¹⁾⁽²⁾
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LVPECL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
f_{CLKout_FS}
f_{CLKout_RS}
Jitter_ADD
Jitter_ADD
Maximum Output
Frequency
Full V_OD Swing^(5)(10)
Maximum Output
Frequency
Reduced V_OD
Swing^{(5) (10)}
Additive RMS Jitter,
Integration Bandwidth
10 kHz to 20
MHz ^{(5) (11) (12)}
Additive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz⁽¹¹⁾
V_OD ≥ 600 mV,
R_L = 100 Ω differential
V_OD ≥ 400 mV,
R_L = 100 Ω differential
Vcco = 2.5 V ± 5%:
R_T = 91 Ω to GND,
Vcco = 3.3 V ± 5%:
R_T = 160 Ω to GND,
R_L = 100 Ω differential
Vcco = 3.3 V,
R_T = 160 Ω to GND,
R_L = 100 Ω differential
Vcco = 3.3 V ± 5%,
R_T = 160 Ω to GND
Vcco = 2.5 V ± 5%,
R_T = 91 Ω to GND
Vcco = 3.3 V ± 5%,
R_T = 160 Ω to GND
Vcco = 2.5 V ± 5%,
R_T = 91 Ω to GND
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
CLKin: 156.25 MHz,
Slew rate ≥ 3 V/ns
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
CLKin: 625 MHz,
Slew rate ≥ 3 V/ns
1.0
1.2
0.75
1.0
1.5
3.1
1.5
2.3
77
54
59
64
30
GHz
GHz
98
fs
78
fs
Jitter_ADD
Additive RMS Jitter with Vcco = 3.3 V,
LVPECL clock source
from LMK03806^(11)(13)
R_T = 160 Ω to GND,
R_L = 100 Ω differential
CLKin: 156.25 MHz,
J_SOURCE = 190 fs RMS
(10 kHz to 1 MHz)
CLKin: 156.25 MHz,
J_SOURCE = 195 fs RMS
(12 kHz to 20 MHz)
20
fs
51
Noise Floor
DUTY
Noise Floor
f_OFFSET ≥ 10 MHz ^{(14) (15)}
Duty Cycle⁽⁵⁾
Vcco = 3.3 V,
R_T = 160 Ω to GND,
R_L = 100 Ω differential
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
CLKin: 625 MHz,
Slew rate ≥ 3 V/ns
50% input clock duty cycle
-162.5
-158.1
45%
-154.4
dBc/Hz
55%
V_OH
Output High Voltage
T_A = 25 °C, DC Measurement,
V_OL
Output Low Voltage
R_T = 50 Ω to Vcco - 2 V
V_OD
Output Voltage Swing⁽⁶⁾
Vcco -
1.2
Vcco -
0.9
Vcco -
0.7
V
Vcco -
2.0
Vcco -
1.75
Vcco -
1.5
V
600
830
1000 mV
(10) See Typical Characteristics for output operation over frequency.
(11) For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (J_ADD) is calculated using Method #1: J_ADD = SQRT(J_OUT2
- J_SOURCE2), where J_OUT is the total RMS jitter measured at the output driver and J_SOURCE is the RMS jitter of the clock source applied to
CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: J_ADD = SQRT(2*10^dBc/10) /
(2*π*f_CLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise
power can be calculated as: dBc = Noise Floor + 10*log₁₀(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz
using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer
to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Typical Characteristics.
(12) 100 MHz and 156.25 MHz input source from Rohde & Schwarz SMA100A Low-Noise Signal Generator and Sine-to-Square-wave
Conversion block.
(13) 156.25 MHz LVPECL clock source from LMK03806 with 20 MHz crystal reference (crystal part number: ECS-200-20-30BU-DU).
J_SOURCE = 190 fs RMS (10 kHz to 1 MHz) and 195 fs RMS (12 kHz to 20 MHz). Refer to the LMK03806 datasheet for more information.
(14) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower
frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.
(15) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input
(LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection.
However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance
at the device outputs.
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