LMK00306_16 Datasheet, PDF (6/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾
V_CC, V_CCO
V_IN
T_STG
T_L
T_J
Supply Voltages
Input Voltage
Storage Temperature
Lead Temperature (solder 4 s)
Junction Temperature
MIN
MAX
UNIT
-0.3
3.6
V
-0.3
(V_CC + 0.3)
V
-65
+150
°C
+260
°C
+150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Machine model (MM)
Charged-device model (CDM), per JEDEC specification JESD22-
C101 ⁽²⁾
VALUE
±2000
±150
±750
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.
6.3 Recommended Operating Conditions
PARAMETER
T_A
Ambient Temperature Range
T_J
Junction Temperature
V_CC
Core Supply Voltage Range
V_CCO
Output Supply Voltage Range ⁽¹⁾⁽²⁾
MIN
-40
3.15
3.3 – 5%
2.5 – 5%
TYP
MAX
UNIT
25
85
°C
125
°C
3.3
3.45
V
3.3
2.5
3.3 + 5%
2.5 + 5%
V
(1) The output supply voltages or pins (V_CCOA, V_CCOB, and V_CCOC) will be called V_CCO in general when no distinction is needed, or when the
output supply can be inferred from the output bank/type.
(2) Vcco should be less than or equal to Vcc (Vcco ≤ Vcc).
6.4 Thermal Information
THERMAL METRIC⁽¹⁾⁽²⁾
NJK0036A
(WQFN)
36 PINS
UNIT
R_θJA
R_{θJC(top) (DAP)}
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
31.8
°C/W
7.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Specification assumes 9 thermal vias connect the die attach pad (DAP) to the embedded copper plane on the 4-layer JEDEC board.
These vias play a key role in improving the thermal performance of the package. It is recommended that the maximum number of vias
be used in the board layout.
6
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