LMK00306_16 Datasheet, PDF (23/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
Driving the Clock Inputs (continued)
CMOS
Driver
VO,PP
Rs
50: Trace
VO,PP/2
V_CC
VBB ~ (VO,PP/2) x 0.5
R_B1
V_CC
50:
LMK
Input
R_B2
0.1 PF
Figure 26. Single-Ended LVCMOS Input, DC Coupling
with Common Mode Biasing
If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external
clock as shown in Figure 27. The input clock should be AC coupled to the OSCin pin, which has an internally-
generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative
input to multiplex an external clock, it is recommended to use either universal input (CLKinX) since it offers
higher operating frequency, better common mode and power supply noise rejection, and greater performance
over supply voltage and temperature variations.
CMOS
Driver
R_S ^{0.1 PF} _{50: Trace}
0.1 PF
OSCin
OSCout
Figure 27. Driving OSCin with a Single-Ended Input
9.2 Crystal Interface
The LMK00306 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The
crystal interface is shown in Figure 28.
C₁
OSCin
XTAL
R_{LIM OSCout}
C₂
Figure 28. Crystal Interface
The load capacitance (C_L) is specific to the crystal, but usually on the order of 18 - 20 pF. While C_L is specified
for the crystal, the OSCin input capacitance (C_IN = 4 pF typical) of the device and PCB stray capacitance (C_STRAY
~ 1~3 pF) can affect the discrete load capacitor values, C₁ and C₂.
For the parallel resonant circuit, the discrete capacitor values can be calculated as follows:
C_L = (C₁ * C₂) / (C₁ + C₂) + C_IN + C_STRAY
(1)
Typically, C₁ = C₂ for optimum symmetry, so Equation 1 can be rewritten in terms of C₁ only:
C_L = C₁₂ / (2 * C₁) + C_IN + C_STRAY
(2)
Finally, solve for C₁:
C₁ = (C_L - C_IN - C_STRAY)*2
(3)
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