LMK00306_16 Datasheet, PDF (28/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
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Termination and Use of Clock Drivers (continued)
When AC coupling an LVPECL driver use a 160 Ω emitter resistor (or 91 Ω for Vcco = 2.5 V) to provide a DC
path to ground and ensure a 50 Ω termination with the proper DC bias level for the receiver. The typical DC bias
voltage for LVPECL receivers is 2 V. If the companion driver is not used, it should be terminated with either a
proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to
measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using
most RF test equipment no DC bias point (0 VDC) is required for safe and proper operation. The internal 50 Ω
termination the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 38.
When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused
driver.
CLKoutX
LVPECL
Driver
CLKoutX*
0.1 PF
0.1 PF
50: Trace
Vcco R_T
3.3V 160:
2.5V 91:
Load
Figure 38. Single-Ended LVPECL Operation, AC Coupling
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