LMK00306_16 Datasheet, PDF (25/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
Termination and Use of Clock Drivers (continued)
For DC coupled operation of an HCSL driver, terminate with 50 Ω to ground near the driver output as shown in
Figure 30. Series resistors, Rs, may be used to limit overshoot due to the fast transient current. Because HCSL
drivers require a DC path to ground, AC coupling is not allowed between the output drivers and the 50 Ω
termination resistors.
CLKoutX ^Rs
HCSL
Driver
Rs
CLKoutX*
50: Traces
HCSL
Receiver
Figure 30. HCSL Operation, DC Coupling
For DC coupled operation of an LVPECL driver, terminate with 50 Ω to Vcco – 2 V as shown in Figure 31.
Alternatively terminate with a Thevenin equivalent circuit as shown in Figure 32 for Vcco (output driver supply
voltage) = 3.3 V and 2.5 V. In the Thevenin equivalent circuit, the resistor dividers set the output termination
voltage (V_TT) to Vcco - 2 V.
Vcco - 2V
CLKoutX
LVPECL
Driver
CLKoutX*
100: Trace
(Differential)
LVPECL
Receiver
Vcco - 2V
Figure 31. Differential LVPECL Operation, DC Coupling
Vcco
CLKoutX
LVPECL
Driver
100: Trace
(Differential)
CLKoutX*
Vcco
3.3V
R_PU
120:
2.5V 250:
R_PD V_TT
82: ~1.3V
62.5: 0.5V
Vcco
LVPECL
Receiver
Figure 32. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent
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