LMK00306_16 Datasheet, PDF (17/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
Typical Characteristics (continued)
Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, T_A = 25 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns.
Consult Table 1 at the end of Typical Characteristics for graph footnotes.
See Note 1 in Graph Notes table
See Note 1 in Graph Notes table
Figure 19. LVDS Phase Noise @ 100 MHz
200 _{20 MHz Crystal}
175 ^{40 MHz Crystal}
150
125
100
75
50
25
0
0 500 1k 1.5k 2k 2.5k 3k 3.5k 4k
RLIM( )
See Notes 2 and 3 in Graph Notes table
Figure 20. HCSL Phase Noise @ 100 MHz
-60 _{20 MHz Crystal, Rlim = 1.5 k}
40 MHz Crystal, Rlim = 1.0 k
-80
-100
-120
-140
-160
-180
10
100 1k 10k 100k 1M 10M
OFFSET FREQUENCY (Hz)
See Notes 2 and 3 in Graph Notes table.
Figure 21. Crystal Power Dissipation vs. R_LIM
Figure 22. LVDS Phase Noise in Crystal Mode
Table 1. Graph Notes
NOTE
(1)
(2)
(3)
The typical RMS jitter values in the plots show the total output RMS jitter (J_OUT) for each output buffer type and the source clock
RMS jitter (J_SOURCE). From these values, the Additive RMS Jitter can be calculated as: J_ADD = SQRT(J_OUT2 - J_SOURCE2).
20 MHz crystal characteristics: Abracon ABL series, AT cut, C_L = 18 pF , C₀ = 4.4 pF measured (7 pF max), ESR = 8.5 Ω
measured (40 Ω max), and Drive Level = 1 mW max (100 µW typical).
40 MHz crystal characteristics: Abracon ABLS2 series, AT cut, C_L = 18 pF , C₀ = 5 pF measured (7 pF max), ESR = 5 Ω
measured (40 Ω max), and Drive Level = 1 mW max (100 µW typical).
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