LMK00306_16 Datasheet, PDF (29/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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10 Power Supply Recommendations
LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
10.1 Power Supply Sequencing
When powering the Vcc and Vcco pins from separate supply rails, it is recommended for the supplies to reach
their regulation point at approximately the same time while ramping up, or reach ground potential at the same
time while ramping down. Using simultaneous or ratiometric power supply sequencing prevents internal current
flow from Vcc to Vcco pins that could occur when Vcc is powered before Vcco.
10.2 Current Consumption and Power Dissipation Calculations
The current consumption values specified in Electrical Characteristics can be used to calculate the total power
dissipation and IC power dissipation for any device configuration. The total V_CC core supply current (I_{CC_TOTAL})
can be calculated using Equation 5:
I_{CC_TOTAL} = I_{CC_CORE} + I_{CC_BANK_A} + I_{CC_BANK_B} + I_{CC_CMOS}
where
• I_{CC_CORE} is the current for core logic and input blocks and depends on selected input (CLKinX or OSCin).
• I_{CC_BANK_A} is the current for Bank A and depends on output type (I_{CC_PECL}, I_{CC_LVDS}, I_{CC_HCSL}, or 0 mA if
disabled).
• I_{CC_BANK_B} is the current for Bank B and depends on output type (I_{CC_PECL}, I_{CC_LVDS}, I_{CC_HCSL}, or 0 mA if
disabled).
• I_{CC_CMOS} is the current for the LVCMOS output (or 0 mA if REFout is disabled).
(5)
Since the output supplies (V_CCOA, V_CCOB, V_CCOC) can be powered from 3 independent voltages, the respective
output supply currents (I_{CCO_BANK_A}, I_{CCO_BANK_B}, and I_{CCO_CMOS}) should be calculated separately.
I_{CCO_BANK} for either Bank A or B can be directly taken from the corresponding output supply current spec
(I_{CCO_PECL}, I_{CCO_LVDS}, or I_{CCO_HCSL}) provided the output loading matches the specified conditions. Otherwise,
I_{CCO_BANK} should be calculated as follows:
I_{CCO_BANK} = I_{BANK_BIAS} + (N * I_{OUT_LOAD})
where
• I_{BANK_BIAS} is the output bank bias current (fixed value).
• I_{OUT_LOAD} is the DC load current per loaded output pair.
• N is the number of loaded output pairs per bank (N = 0 to 3).
(6)
Table 6 shows the typical I_{BANK_BIAS} values and I_{OUT_LOAD} expressions for LVPECL, LVDS, and HCSL.
For LVPECL, it is possible to use a larger termination resistor (R_T) to ground instead of terminating with 50 Ω to
V_TT = Vcco - 2 V; this technique is commonly used to eliminate the extra termination voltage supply (V_TT) and
potentially reduce device power dissipation at the expense of lower output swing. For example, when Vcco is 3.3
V, a R_T value of 160 Ω to ground will eliminate the 1.3 V termination supply without sacrificing much output
swing. In this case, the typical I_{OUT_LOAD} is 25 mA, so I_{CCO_PECL} for a fully-loaded bank reduces to 95 mA (vs. 100
mA with 50 Ω resistors to Vcco – 2 V).
CURRENT PARAMETER
I_{BANK_BIAS}
I_{OUT_LOAD}
Table 6. Typical Output Bank Bias and Load Currents
LVPECL
20 mA
(V_OH - V_TT)/R_T + (V_OL - V_TT)/R_T
LVDS
17.4 mA
0 mA
(No DC load current)
HCSL
3.6 mA
V_OH/R_T
Once the current consumption is known for each supply, the total power dissipation (P_TOTAL) can be calculated
as:
P_TOTAL = (V_CC*I_{CC_TOTAL}) + (V_CCOA*I_{CCO_BANK_A}) + (V_CCOB*I_{CCO_BANK_B}) + (V_CCOC*I_{CCO_CMOS})
(7)
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