LMK00306_16 Datasheet, PDF (1/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
LMK00306 3-GHz 6-Output Ultra-Low Additive Jitter
Differential Clock Buffer/Level Translator
1 Features
•1 3:1 Input Multiplexer
– Two Universal Inputs Operate up to 3.1 GHz
and Accept LVPECL, LVDS, CML, SSTL,
HSTL, HCSL, or Single-Ended Clocks
– One Crystal Input Accepts a 10 to 40 MHz
Crystal or Single-Ended Clock
• Two Banks with 3 Differential Outputs Each
– LVPECL, LVDS, HCSL, or Hi-Z (Selectable
Per Bank)
– LVPECL Additive Jitter with LMK03806 Clock
Source at 156.25 MHz:
– 20 fs RMS (10 kHz to 1 MHz)
– 51 fs RMS (12 kHz to 20 MHz)
• High PSRR: -65 / -76 dBc (LVPECL/LVDS) at
156.25 MHz
• LVCMOS Output with Synchronous Enable Input
• Pin-Controlled Configuration
• V_CC Core Supply: 3.3 V ± 5%
• 3 Independent V_CCO Output Supplies: 3.3 V/2.5 V
± 5%
• Industrial Temperature Range: -40°C to +85°C
• 36-lead WQFN (6 mm × 6 mm)
2 Applications
• Clock Distribution and Level Translation for ADCs,
DACs, Multi-Gigabit Ethernet, XAUI, Fibre
Channel, SATA/SAS, SONET/SDH, CPRI, High-
Frequency Backplanes
• Switches, Routers, Line Cards, Timing Cards
• Servers, Computing, PCI Express (PCIe 3.0)
• Remote Radio Units and Baseband Units
3 Description
The LMK00306 is a 3-GHz, 6-output differential
fanout buffer intended for high-frequency, low-jitter
clock/data distribution and level translation. The input
clock can be selected from two universal inputs or
one crystal input. The selected input clock is
distributed to two banks of 3 differential outputs and
one LVCMOS output. Both differential output banks
can be independently configured as LVPECL, LVDS,
or HCSL drivers, or disabled. The LVCMOS output
has a synchronous enable input for runt-pulse-free
operation when enabled or disabled. The LMK00306
operates from a 3.3 V core supply and 3 independent
3.3 V/2.5 V output supplies.
The LMK00306 provides high performance,
versatility, and power efficiency, making it ideal for
replacing fixed-output buffer devices while increasing
timing margin in the system.
Functional Block Diagram
VCC VCCOA VCCOB VCCOC
2
CLKoutA_TYPE[1:0]
2
CLKin_SEL[1:0]
Universal Inputs
(Differential/
Single-Ended)
CLKin0
CLKin0*
CLKin1
CLKin1*
OSCin
Crystal
OSCout
2
CLKoutB_TYPE[1:0]
REFout_EN
3:1
MUX
SYNC
VCCOA
VCCOB
VCCOC
CLKoutA0
CLKoutA0*
CLKoutA1
CLKoutA1*
CLKoutA2
CLKoutA2*
Bank A
(LVPECL, LVDS,
HCSL, or Hi-Z)
CLKoutB0
CLKoutB0*
CLKoutB1
CLKoutB1*
CLKoutB2
CLKoutB2*
Bank B
(LVPECL, LVDS,
HCSL, or Hi-Z)
REFout (LVCMOS)
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMK00306
WQFN (36)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
LVPECL Output Swing (V_OD) vs. Frequency
1.0 _{Vcco=2.5 V, Rterm=91}
0.9 ^{Vcco=3.3 V, Rterm=160}
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
100
1000
FREQUENCY (MHz)
10000
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.