LMK00306_16 Datasheet, PDF (24/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
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Crystal Interface (continued)
Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the
crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power
dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the
crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient
level necessary to start-up and maintain steady-state operation.
The power dissipated in the crystal, P_XTAL, can be computed by:
P_XTAL = I_RMS2 * R_ESR*(1 + C₀/C_L)²
where
• I_RMS is the RMS current through the crystal.
• R_ESR is the max. equivalent series resistance specified for the crystal
• C_L is the load capacitance specified for the crystal
• C₀ is the min. shunt capacitance specified for the crystal
(4)
I_RMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal
connected to OSCout with the oscillation circuit active.
As shown in Figure 28 , an external resistor, R_LIM, can be used to limit the crystal drive level, if necessary. If the
power dissipated in the selected crystal is higher than the drive level specified for the crystal with R_LIM shorted,
then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the
crystal is less than the drive level with R_LIM shorted, then a zero value for R_LIM can be used. As a starting point, a
suggested value for R_LIM is 1.5 kΩ.
9.3 Termination and Use of Clock Drivers
When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:
• Transmission line theory should be followed for good impedance matching to prevent reflections.
• Clock drivers should be presented with the proper loads.
– LVDS outputs are current drivers and require a closed current loop.
– HCSL drivers are switched current outputs and require a DC path to ground via 50 Ω termination.
– LVPECL outputs are open emitter and require a DC path to ground.
• Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage)
for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage
level; in this case, the signal should normally be AC coupled.
It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the above
guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best
termination and coupling method to be sure the receiver is biased at the optimum DC voltage (common mode
voltage).
9.3.1 Termination for DC Coupled Differential Operation
For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS receiver as
shown in Figure 29.
CLKoutX
LVDS
Driver
100: Trace
(Differential)
LVDS
Receiver
CLKoutX*
Figure 29. Differential LVDS Operation, DC Coupling,
No Biasing by the Receiver
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