LMK00306_16 Datasheet, PDF (5/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
NO.
DAP
1, 19, 28
2, 5
3, 4
6, 7
8, 9
10, 36
11, 32
12
13
14, 17
15, 16
18, 29
20, 21
22, 23
24, 27
25, 26
30, 31
33
34
35
PIN
NAME
DAP
GND
V_CCOA
CLKoutA0, CLKoutA0*
CLKoutA1, CLKoutA1*
CLKoutA2, CLKoutA2*
CLKoutA_TYPE0, CLKoutA_TYPE1
Vcc
OSCin
OSCout
CLKin_SEL0, CLKin_SEL1
CLKin0, CLKin0*
CLKoutB_TYPE0, CLKoutB_TYPE1
CLKoutB2*, CLKoutB2
CLKoutB1*, CLKoutB1
V_CCOB
CLKoutB0*, CLKoutB0
CLKin1*, CLKin1
REFout
V_CCOC
REFout_EN
Pin Functions⁽¹⁾
TYPE
DESCRIPTION
GND
GND
PWR
O
O
O
I
PWR
I
O
I
I
I
O
O
PWR
O
I
O
PWR
I
Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
Ground
Power supply for Bank A Output buffers. V_CCOA can operate from 3.3 V or
2.5 V. The V_CCOA pins are internally tied together. Bypass with a 0.1 uF
low-ESR capacitor placed very close to each Vcco pin. ⁽²⁾
Differential clock output A0. Output type set by CLKoutA_TYPE pins.
Differential clock output A1. Output type set by CLKoutA_TYPE pins.
Differential clock output A2. Output type set by CLKoutA_TYPE pins.
Bank A output buffer type selection pins ⁽³⁾
Power supply for Core and Input buffer blocks. The Vcc supply operates
from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to
each Vcc pin.
Input for crystal. Can also be driven by a XO, TCXO, or other external
single-ended clock.
Output for crystal. Leave OSCout floating if OSCin is driven by a single-
ended clock.
Clock input selection pins ⁽³⁾
Universal clock input 0 (differential/single-ended)
Bank B output buffer type selection pins ⁽³⁾
Differential clock output B2. Output type set by CLKoutB_TYPE pins.
Differential clock output B1. Output type set by CLKoutB_TYPE pins.
Power supply for Bank B Output buffers. V_CCOB can operate from 3.3 V or
2.5 V. The V_CCOB pins are internally tied together. Bypass with a 0.1 uF
low-ESR capacitor placed very close to each Vcco pin. ⁽²⁾
Differential clock output B0. Output type set by CLKoutB_TYPE pins.
Universal clock input 1 (differential/single-ended)
LVCMOS reference output. Enable output by pulling REFout_EN pin high.
Power supply for REFout Output buffer. V_CCOC can operate from 3.3 V or
2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each
Vcco pin. ⁽²⁾
REFout enable input. Enable signal is internally synchronized to selected
clock input. ⁽³⁾
(1) Any unused output pins should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if
connected to a transmission line, or disabled/Hi-Z if possible. See Clock Outputs for output configuration or Termination and Use of
Clock Drivers for output interface and termination techniques.
(2) The output supply voltages or pins (V_CCOA, V_CCOB, and V_CCOC) will be called V_CCO in general when no distinction is needed, or when the
output supply can be inferred from the output bank/type.
(3) CMOS control input with internal pull-down resistor.
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