LMK00306_16 Datasheet, PDF (11/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
Electrical Characteristics (continued)
Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ T_A ≤ 85 °C, CLKin driven
differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A
= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. ⁽¹⁾⁽²⁾
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
f_CLKout
Output Frequency
Range ⁽⁵⁾
R_L = 50 Ω to GND, C_L ≤ 5 pF
DC
400 MHz
Jitter_{ADD_PCIe}
Additive RMS Phase
Jitter for PCIe 3.0⁽⁵⁾
PCIe Gen 3,
PLL BW = 2–5 MHz,
CDR = 10 MHz
CLKin: 100 MHz,
Slew rate ≥ 0.6 V/ns
0.03
0.15 ps
Jitter_ADD
Additive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz⁽¹¹⁾
Vcco = 3.3 V,
R_T = 50 Ω to GND
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
77
fs
86
Noise Floor
DUTY
Noise Floor
f_OFFSET ≥ 10 MHz^{(14) (15)}
Duty Cycle⁽⁵⁾
Vcco = 3.3 V,
R_T = 50 Ω to GND
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
50% input clock duty cycle
-161.3
45%
-156.3
dBc/Hz
55%
V_OH
V_OL
Output High Voltage
Output Low Voltage
T_A = 25 °C, DC Measurement, R_T = 50 Ω to GND
520
810
920 mV
-150
0.5
150 mV
V_CROSS
ΔV_CROSS
Absolute Crossing
Voltage ^{(5) (16)}
Total Variation of
V_CROSS ^{(5) (16)}
R_L = 50 Ω to GND, C_L ≤ 5 pF
160
350
460 mV
140 mV
t_R
Output Rise Time
20% to 80%^(7)(16)
250 MHz, Uniform transmission line up to 10
t_F
Output Fall Time
80% to 20%^(7)(16)
inches with 50-Ω characteristic impedance, R_L = 50
Ω to GND, C_L ≤ 5 pF
300
500 ps
300
500 ps
(16) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.
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