LMK00306_16 Datasheet, PDF (7/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
6.5 Electrical Characteristics
Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ T_A ≤ 85 °C, CLKin driven
differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A
= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. ⁽¹⁾⁽²⁾
PARAMETER
CURRENT CONSUMPTION⁽³⁾
TEST CONDITIONS
MIN
TYP
MAX UNIT
I_{CC_CORE}
Core Supply Current, All ^{CLKinX selected}
Outputs Disabled
OSCin selected
8.5
10.5 mA
10
13.5 mA
I_{CC_PECL}
Additive Core Supply
Current, Per LVPECL
Bank Enabled
20
26.5 mA
I_{CC_LVDS}
Additive Core Supply
Current, Per LVDS Bank
Enabled
24
29.5 mA
I_{CC_HCSL}
Additive Core Supply
Current, Per HCSL Bank
Enabled
29
35 mA
I_{CC_CMOS}
Additive Core Supply
Current, LVCMOS
Output Enabled
3.5
5.5 mA
I_{CCO_PECL}
Additive Output Supply
Current, Per LVPECL
Bank Enabled
Includes Output Bank Bias and Load Currents,
R_T = 50 Ω to Vcco - 2V on all outputs in bank
100
123 mA
I_{CCO_LVDS}
Additive Output Supply
Current, Per LVDS Bank
Enabled
20
27.5 mA
I_{CCO_HCSL}
Additive Output Supply
Current, Per HCSL Bank
Enabled
Includes Output Bank Bias and Load Currents,
R_T = 50 Ω on all outputs in bank
50
65 mA
I_{CCO_CMOS}
Additive Output Supply
Current, LVCMOS
Output Enabled
200 MHz, C_L = 5 pF
Vcco = 3.3 V ± 5%
Vcco = 2.5 V ± 5%
9
10 mA
7
8 mA
POWER SUPPLY RIPPLE REJECTION (PSRR)
PSRR_PECL
Ripple-Induced Phase
Spur Level Differential
LVPECL Output⁽⁴⁾
156.25 MHz
312.5 MHz
-65
dBc
-63
PSRR_LVDS
Ripple-Induced Phase
Spur Level Differential
LVDS Output⁽⁴⁾
100 kHz, 100 mVpp
156.25 MHz
Ripple Injected on Vcco,
Vcco = 2.5 V
312.5 MHz
-76
dBc
-74
PSRR_HCSL
Ripple-Induced Phase
Spur Level Differential
HCSL Output⁽⁴⁾
156.25 MHz
312.5 MHz
-72
dBc
-63
CMOS CONTROL INPUTS (CLKin_SELn, CLKoutX_TYPEn, REFout_EN)
V_IH
High-Level Input Voltage
V_IL
Low-Level Input Voltage
I_IH
High-Level Input Current V_IH = Vcc, Internal pull-down resistor
I_IL
Low-Level Input Current V_IL = 0 V, Internal pull-down resistor
1.6
GND
-5
Vcc V
0.4 V
50 µA
0.1
µA
(1) The output supply voltages or pins (V_CCOA, V_CCOB, and V_CCOC) will be called V_CCO in general when no distinction is needed, or when the
output supply can be inferred from the output bank/type.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) See Power Supply Recommendations for more information on current consumption and power dissipation calculations.
(4) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output
when a single-tone sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index
modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as
follows: DJ (ps pk-pk) = [ (2 * 10^{(PSRR / 20)}) / (π * f_CLK) ] * 1E12
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