LMK00306_16 Datasheet, PDF (19/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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8 Detailed Description
LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
8.1 Overview
The LMK00306 is a 6-output differential clock fanout buffer with low additive jitter that can operate up to 3.1 GHz.
It features a 3:1 input multiplexer with an optional crystal oscillator input, two banks of 3 differential outputs with
multi-mode buffers (LVPECL, LVDS, HCSL, or Hi-Z), one LVCMOS output, and 3 independent output buffer
supplies. The input selection and output buffer modes are controlled via pin strapping. The device is offered in a
36-pin WQFN package and leverages much of the high-speed, low-noise circuit design employed in the
LMK04800 family of clock conditioners.
8.2 Functional Block Diagram
CLKoutA_TYPE[1:0]
CLKin_SEL[1:0]
V_CC V_CCOA V_CCOB V_CCOC
2
V_CCOA
2
Universal Inputs
(Differential/
Single-Ended)
CLKin0
CLKin0*
CLKin1
CLKin1*
OSCin
Crystal
OSCout
2
CLKoutB_TYPE[1:0]
REFout_EN
3:1
MUX
V_CCOB
SYNC
V_CCOC
CLKoutA0
CLKoutA0*
CLKoutA1
CLKoutA1*
CLKoutA2
CLKoutA2*
Bank A
(LVPECL, LVDS,
HCSL, or Hi-Z)
CLKoutB0
CLKoutB0*
CLKoutB1
CLKoutB1*
CLKoutB2
CLKoutB2*
Bank B
(LVPECL, LVDS,
HCSL, or Hi-Z)
REFout (LVCMOS)
GND
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