LMK00306_16 Datasheet, PDF (8/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
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Electrical Characteristics (continued)
Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ T_A ≤ 85 °C, CLKin driven
differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A
= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. ⁽¹⁾⁽²⁾
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*)
Functional up to 3.1 GHz
f_CLKin
Input Frequency
Range ⁽⁵⁾
Output frequency range and timing specified per
output type (refer to LVPECL, LVDS, HCSL,
DC
LVCMOS output specifications)
3.1 GHz
V_IHD
Differential Input High
Voltage
Vcc V
V_ILD
Differential Input Low
Voltage
CLKin driven differentially
GND
V
V_ID
Differential Input Voltage
Swing ⁽⁶⁾
0.15
1.3 V
V_CMD
V_IH
Differential Input
Common Mode Voltage
Single-Ended Input High
Voltage
V_ID = 150 mV
V_ID = 350 mV
V_ID = 800 mV
0.25
Vcc - 1.2
0.25
Vcc - 1.1 V
0.25
Vcc -0.9
Vcc V
V_IL
V_{I_SE}
Single-Ended Input Low
Voltage
Single-Ended Input
Voltage Swing⁽⁷⁾⁽⁸⁾
CLKinX driven single-ended (AC or DC coupled),
CLKinX* AC coupled to GND or externally biased
within V_CM range
GND
0.3
V
2 Vpp
V_CM
Single-Ended Input
Common Mode Voltage
0.25
Vcc - 1.2 V
ISO_MUX
Mux Isolation, CLKin0 to f_OFFSET > 50 kHz,
CLKin1
P_CLKinX = 0 dBm
CRYSTAL INTERFACE (OSCin, OSCout)
f_CLKin0 = 100 MHz
f_CLKin0 = 200 MHz
f_CLKin0 = 500 MHz
f_CLKin0 = 1000 MHz
-84
-82
dBc
-71
-65
F_CLK
External Clock
Frequency Range⁽⁵⁾
OSCin driven single-ended, OSCout floating
250 MHz
F_XTAL
Crystal Frequency
Range
Fundamental mode crystal
ESR ≤ 200 Ω (10 to 30 MHz)
ESR ≤ 125 Ω (30 to 40 MHz)⁽⁹⁾
10
40 MHz
C_IN
OSCin Input
Capacitance
4
pF
(5) Specification is ensured by characterization and is not tested in production.
(6) See Differential Voltage Measurement Terminology for definition of V_ID and V_OD voltages.
(7) Parameter is specified by design, not tested in production.
(8) For clock input frequency ≥ 100 MHz, CLKinX can be driven with single-ended (LVCMOS) input swing up to 3.3 Vpp. For clock input
frequency < 100 MHz, the single-ended input swing should be limited to 2 Vpp max to prevent input saturation (refer to Driving the Clock
Inputs for interfacing 2.5 V/3.3 V LVCMOS clock input < 100 MHz to CLKinX).
(9) The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for
the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal
Interface for crystal drive level considerations.
8
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