LMK00306_16 Datasheet, PDF (15/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
Typical Characteristics (continued)
Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, T_A = 25 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns.
Consult Table 1 at the end of Typical Characteristics for graph footnotes.
1.0
1.00 _{Vcco=3.3 V, AC coupled, 50 load}
0.75 ^{Vcco=2.5 V, AC coupled, 50 load}
0.8
0.50
0.6
0.25
0.4
0.00
-0.25
0.2
-0.50
0.0
-0.75
-0.2
0
1
2
3
4
5
TIME (ns)
-1.00
0123456
TIME (ns)
Figure 7. HCSL Output Swing @ 250 MHz
-140
-145
-150
LVPECL
LVDS
HCSL
LVCMOS
CLKin Source
Fclk=100 MHz
Foffset=20 MHz
-155
-160
-165
-170
0.5 1.0 1.5 2.0 2.5 3.0 3.5
DIFFERENTIAL INPUT SLEW RATE (V/ns)
Figure 8. LVCMOS Output Swing @ 250 MHz
-135
-140
LVPECL
LVDS
HCSL
CLKin Source
Fclk=156.25 MHz
Foffset=20 MHz
-145
-150
-155
-160
-165
0.5 1.0 1.5 2.0 2.5 3.0 3.5
DIFFERENTIAL INPUT SLEW RATE (V/ns)
Figure 9. Noise Floor vs. CLKin Slew Rate @ 100 MHz
-135
-140
LVPECL
LVDS
CLKin Source
Fclk=625 MHz
Foffset=20 MHz
-145
-150
-155
-160
-165
0.5 1.0 1.5 2.0 2.5 3.0 3.5
DIFFERENTIAL INPUT SLEW RATE (V/ns)
Figure 11. Noise Floor vs. CLKin Slew Rate @ 625 MHz
Figure 10. Noise Floor vs. CLKin Slew Rate @ 156.25 MHz
400 _LVPECL
350
LVDS
HCSL
LVCMOS
Fclk=100 MHz
Int. BW=1-20 MHz
300 CLKin Source
250
200
150
100
50
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
DIFFERENTIAL INPUT SLEW RATE (V/ns)
See Note 1 in Graph Notes
Figure 12. RMS Jitter vs. CLKin Slew Rate @ 100 MHz
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