LMK00306_16 Datasheet, PDF (31/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
Power Supply Bypassing (continued)
For the LMK00306, power supply ripple rejection, or PSRR, was measured as the single-sideband phase spur
level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vcco supply. The
PSRR test setup is shown in Figure 39.
Ripple
Source
Clock
Source
Bias-Tee
Vcco
Vcc
IN+
OUT+
IC
IN-
OUT-
DUT Board
Power
Supplies
Limiting
Amp
OUT
Scope
Phase Noise
Analyzer
Measure 100 mV_PP
ripple on Vcco at IC
Measure single
sideband phase spur
power in dBc
Figure 39. PSRR Test Setup
A signal generator was used to inject a sinusoidal signal onto the Vcco supply of the DUT board, and the peak-
to-peak ripple amplitude was measured at the Vcco pins of the device. A limiting amplifier was used to remove
amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise
analyzer. The phase spur level measurements were taken for clock frequencies of 156.25 MHz and 312.5 MHz
under the following power supply ripple conditions:
• Ripple amplitude: 100 mVpp on Vcco = 2.5 V
• Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz
Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ)
can be calculated using the measured single-sideband phase spur level (PSRR) as follows:
DJ (ps pk-pk) = [(2*10^{(PSRR / 20)}) / (π*f_CLK)] * 10¹²
(12)
The “PSRR vs. Ripple Frequency” plots in Typical Characteristics show the ripple-induced phase spur levels for
the differential output types at 156.25 MHz and 312.5 MHz . The LMK00306 exhibits very good and well-behaved
PSRR characteristics across the ripple frequency range for all differential output types. The phase spur levels for
LVPECL are below -64 dBc at 156.25 MHz and below -62 dBc at 312.5 MHz. Using Equation 12, these phase
spur levels translate to Deterministic Jitter values of 2.57 ps pk-pk at 156.25 MHz and 1.62 ps pk-pk at 312.5
MHz. Testing has shown that the PSRR performance of the device improves for Vcco = 3.3 V under the same
ripple amplitude and frequency conditions.
10.4 Thermal Management
Power dissipation in the LMK00306 device can be high enough to require attention to thermal management. For
reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an
estimate, T_A (ambient temperature) plus device power dissipation times R_θJA should not exceed 125 °C.
The package of the device has an exposed pad that provides the primary heat removal path as well as excellent
electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal
land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the
package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.
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