LMK00306_16 Datasheet, PDF (27/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

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Termination and Use of Clock Drivers (continued)
LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
CLKoutX
LVPECL
Driver
CLKoutX*
Vcco R_T R_PU R_PD V_BB
3.3V 160: 82: 120: 2V
2.5V 91: 62.5: 250: 2V
Vcco
0.1 PF
0.1 PF
100: Trace
(Differential)
LVPECL
Reciever
Vcco
Figure 35. Differential LVPECL Operation, AC Coupling,
Thevenin Equivalent
9.3.3 Termination for Single-Ended Operation
A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an
unbalanced, single-ended signal.
It is possible to use an LVPECL driver as one or two separate 800 mV p-p signals. When DC coupling one of the
LMK00306 LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminate the unused driver. When
DC coupling on of the LMK00306 LVPECL drivers, the termination should be 50 Ω to Vcco - 2 V as shown in
Figure 36. The Thevenin equivalent circuit is also a valid termination as shown in Figure 37 for Vcco = 3.3 V.
Vcco - 2V
CLKoutX
LVPECL
Driver
Vcco - 2V
50: Trace
Load
CLKoutX* _50:
Figure 36. Single-Ended LVPECL Operation, DC Coupling
Vcco
CLKoutX
LVPECL
Driver
Vcco
CLKoutX*
(unused)
50: Trace
Vcco
3.3V
2.5V
R_PU
120:
250:
R_PD V_TT
82: ~1.3V
62.5: 0.5V
Load
Figure 37. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent
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