LMK00306_16 Datasheet, PDF (32/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
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Thermal Management (continued)
A recommended land and via pattern is shown in Figure 40. More information on soldering WQFN packages can
be obtained at: http://www.ti.com/packaging.
4.6 mm, min
0.2 mm,
typ
1.2 mm,
typ
Figure 40. Recommended Land and Via Pattern
To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground
plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite
side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but
should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in
Figure 40 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively
dissipated.
32
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