LMK00306_16 Datasheet, PDF (30/39 Pages) Texas Instruments – 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

LMK00306
SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016
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If the device is configured with LVPECL or HCSL outputs, then it is also necessary to calculate the power
dissipated in any termination resistors (P_{RT_ PECL} and P_{RT_HCSL}) and in any LVPECL termination voltages
(P_{VTT_PECL}). The external power dissipation values can be calculated as follows:
P_{RT_PECL} (per LVPECL pair) = (V_OH - V_TT)²/R_T + (V_OL - V_TT)²/R_T
(8)
P_{VTT_PECL} (per LVPECL pair) = V_TT * [(V_OH - V_TT)/R_T + (V_OL - V_TT)/R_T]
(9)
P_{RT_HCSL} (per HCSL pair) = V_OH2 / R_T
(10)
Finally, the IC power dissipation (P_DEVICE) can be computed by subtracting the external power dissipation values
from P_TOTAL as follows:
P_DEVICE = P_TOTAL - N₁*(P_{RT_PECL} + P_{VTT_PECL}) - N₂*P_{RT_HCSL}
where
• N₁ is the number of LVPECL output pairs with termination resistors to V_TT (usually Vcco - 2 V or GND).
• N₂ is the number of HCSL output pairs with termination resistors to GND.
(11)
10.2.1 Power Dissipation Example: Worst-Case Dissipation
This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power
dissipation. In this case, the maximum supply voltage and supply current values specified in Electrical
Characteristics are used.
• V_CC = V_CCO = 3.465 V. Max I_CC and I_CCO values.
• CLKin0/CLKin0* input is selected.
• Banks A and B are configured for LVPECL: all outputs terminated with 50 Ω to V_T = Vcco - 2 V.
• REFout is enabled with 5 pF load.
• T_A = 85 °C
Using the power calculations from the previous section and maximum supply current specifications, we can
compute P_TOTAL and P_DEVICE.
• From Equation 5: I_{CC_TOTAL} = 10.5 mA + 22.5 mA + 22.5 mA + 5.5 mA = 61 mA
• From I_{CCO_PECL} max spec: I_{CCO_BANK_A} = I_{CCO_BANK_B} = 115 mA
• From Equation 7: P_TOTAL = 3.465 V * (61 mA + 115 mA + 115 mA + 10 mA) = 1043 mW
• From Equation 8: P_{RT_PECL} = ((2.57 V - 1.47 V)²/50 Ω) + ((1.72 V - 1.47 V)²/50 Ω) = 25.5 mW (per output pair)
• From Equation 9: P_{VTT_PECL} = 1.47 V * [ ((2.57 V - 1.47 V) / 50 Ω) + ((1.72 V - 1.47 V) / 50 Ω) ] = 39.5 mW
(per output pair)
• From Equation 10: P_{RT_HCSL} = 0 mW (no HCSL outputs)
• From Equation 11: P_DEVICE = 1043 mW - (6 * (25.5 mW + 39.5 mW)) - 0 mW = 653 mW
In this worst-case example, the IC device will dissipate about 653 mW or 63% of the total power (1043 mW),
while the remaining 37% will be dissipated in the LVPECL emitter resistors (153 mW for 6 pairs) and termination
voltage (237 mW into Vcco - 2 V). Based on θ_JA of 31.8 °C/W, the estimated die junction temperature would be
about 21 °C above ambient, or 106 °C when T_A = 85 °C.
10.3 Power Supply Bypassing
The Vcc and Vcco power supplies should have a high-frequency bypass capacitor, such as 0.1 uF or 0.01 uF,
placed very close to each supply pin. 1 uF to 10 uF decoupling capacitors should also be placed nearby the
device between the supply and ground planes. All bypass and decoupling capacitors should have short
connections to the supply and ground plane through a short trace or via to minimize series inductance.
10.3.1 Power Supply Ripple Rejection
In practical system applications, power supply noise (ripple) can be generated from switching power supplies,
digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to
understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is
applied to the power supply of a clock distribution device, such as LMK00306, it can produce narrow-band phase
modulation as well as amplitude modulation on the clock output (carrier). In the single-side band phase noise
spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in
dBc).
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