LM3S6100 Datasheet, PDF (9/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Stellaris^® LM3S6100 Microcontroller
List of Figures
Figure 1-1. Stellaris LM3S6100 Microcontroller High-Level Block Diagram ............................... 35
Figure 2-1. CPU Block Diagram ............................................................................................. 43
Figure 2-2. TPIU Block Diagram ............................................................................................ 44
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 46
Figure 2-4. Bit-Band Mapping ................................................................................................ 66
Figure 2-5. Data Storage ....................................................................................................... 67
Figure 2-6. Vector Table ........................................................................................................ 72
Figure 2-7. Exception Stack Frame ........................................................................................ 74
Figure 3-1. SRD Use Example ............................................................................................... 89
Figure 4-1. JTAG Module Block Diagram .............................................................................. 148
Figure 4-2. Test Access Port State Machine ......................................................................... 152
Figure 4-3. IDCODE Register Format ................................................................................... 158
Figure 4-4. BYPASS Register Format ................................................................................... 158
Figure 4-5. Boundary Scan Register Format ......................................................................... 159
Figure 5-1. Basic RST Configuration .................................................................................... 162
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 163
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 163
Figure 5-4. Power Architecture ............................................................................................ 166
Figure 5-5. Main Clock Tree ................................................................................................ 168
Figure 6-1. Flash Block Diagram .......................................................................................... 216
Figure 7-1. GPIO Port Block Diagram ................................................................................... 247
Figure 7-2. GPIODATA Write Example ................................................................................. 248
Figure 7-3. GPIODATA Read Example ................................................................................. 248
Figure 8-1. GPTM Module Block Diagram ............................................................................ 288
Figure 8-2. 16-Bit Input Edge Count Mode Example .............................................................. 292
Figure 8-3. 16-Bit Input Edge Time Mode Example ............................................................... 293
Figure 8-4. 16-Bit PWM Mode Example ................................................................................ 294
Figure 9-1. WDT Module Block Diagram .............................................................................. 324
Figure 10-1. UART Module Block Diagram ............................................................................. 348
Figure 10-2. UART Character Frame ..................................................................................... 349
Figure 10-3. IrDA Data Modulation ......................................................................................... 351
Figure 11-1. SSI Module Block Diagram ................................................................................. 389
Figure 11-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 392
Figure 11-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 393
Figure 11-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 393
Figure 11-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 394
Figure 11-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 395
Figure 11-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 395
Figure 11-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 396
Figure 11-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 397
Figure 11-10. MICROWIRE Frame Format (Single Frame) ........................................................ 397
Figure 11-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 398
Figure 11-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 399
Figure 12-1. Ethernet Controller ............................................................................................. 428
Figure 12-2. Ethernet Controller Block Diagram ...................................................................... 428
Figure 12-3. Ethernet Frame ................................................................................................. 430
June 18, 2012
9
Texas Instruments-Production Data