LM3S6100 Datasheet, PDF (442/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Ethernet Controller
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the
interrupt, while setting the bit enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Bit/Field
31:7
6
5
4
3
2
1
0
Name
reserved
PHYINTM
MDINTM
RXERM
FOVM
TXEMPM
TXERM
RXINTM
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
Mask PHY Interrupt
Clearing this bit masks the PHYINT bit in the MACRIS register from
being set.
1
Mask MII Transaction Complete
Clearing this bit masks the MDINT bit in the MACRIS register from being
set.
1
Mask Receive Error
Clearing this bit masks the RXER bit in the MACRIS register from being
set.
1
Mask FIFO Overrun
Clearing this bit masks the FOV bit in the MACRIS register from being
set.
1
Mask Transmit FIFO Empty
Clearing this bit masks the TXEMP bit in the MACRIS register from being
set.
1
Mask Transmit Error
Clearing this bit masks the TXER bit in the MACRIS register from being
set.
1
Mask Packet Received
Clearing this bit masks the RXINT bit in the MACRIS register from being
set.
442
June 18, 2012
Texas Instruments-Production Data