LM3S6100 Datasheet, PDF (19/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Stellaris^® LM3S6100 Microcontroller
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 421
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 422
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 423
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 424
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 425
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 426
Ethernet Controller ...................................................................................................................... 427
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... 439
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 442
Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 443
Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 444
Register 5: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 445
Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 447
Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 448
Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 449
Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 451
Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 452
Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 453
Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 454
Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 455
Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 456
Register 15: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 457
Register 16: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 459
Register 17: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 461
Register 18: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 462
Register 19: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 463
Register 20: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 465
Register 21: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 466
Register 22: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 467
Register 23: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 469
Register 24: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 471
Register 25: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 472
Register 26: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 473
Register 27: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 474
Analog Comparator ..................................................................................................................... 475
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 480
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 481
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 482
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 483
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 484
Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 485
June 18, 2012
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