LM3S6100 Datasheet, PDF (18/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Table of Contents
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 341
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 342
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 343
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 344
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 345
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 346
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 347
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 356
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 358
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 360
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 362
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 363
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 364
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 365
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 367
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 369
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 371
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 373
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 374
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 375
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 377
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 378
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 379
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 380
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 381
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 382
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 383
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 384
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 385
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 386
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 387
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 388
Synchronous Serial Interface (SSI) ............................................................................................ 389
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 402
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 404
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 406
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 407
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 409
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 410
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 412
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 413
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 414
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 415
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 416
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 417
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 418
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 419
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 420
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June 18, 2012
Texas Instruments-Production Data