LM3S6100 Datasheet, PDF (503/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Stellaris^® LM3S6100 Microcontroller
Table 15-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
M11
OSC1
O
Analog Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
M12
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.2.2 Signals by Signal Name
Table 15-6. Signals by Signal Name
Pin Name
C0+
C0-
C0o
CCP0
CCP1
CCP2
CCP3
CMOD0
Pin Number
A7
A6
B7
E12
L6
D12
M2
E11
Pin Type
I
I
O
I/O
I/O
I/O
I/O
I
CMOD1
B10
I
ERBIAS
K3
I
GND
GNDA
B6
-
C4
C5
F10
F11
F12
H3
J3
J10
K5
K6
K10
L10
A5
-
B5
GNDPHY
LDO
C8
-
C9
K4
E3
-
LED0
LED1
J12
O
J11
O
Buffer Type^a Description
Analog Analog comparator 0 positive input.
Analog Analog comparator 0 negative input.
TTL
Analog comparator 0 output.
TTL
Capture/Compare/PWM 0.
TTL
Capture/Compare/PWM 1.
TTL
Capture/Compare/PWM 2.
TTL
Capture/Compare/PWM 3.
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
Analog
12.4-kΩ resistor (1% precision) used internally for Ethernet
PHY.
Power Ground reference for logic and I/O pins.
Power
Power
The ground reference for the analog circuits ( Analog
Comparators, etc.). These are separated from GND to
minimize the electrical noise contained on VDD from affecting
the analog functions.
GND of the Ethernet PHY.
Power
TTL
TTL
Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or
greater. The LDO pin must also be connected to the VDD25
pins at the board level in addition to the decoupling
capacitor(s).
Ethernet LED 0.
Ethernet LED 1.
June 18, 2012
503
Texas Instruments-Production Data