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LM3S6100 Datasheet, PDF (22/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller | |||
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Revision History
Table 1. Revision History (continued)
Date
January 2010
Revision Description
6712 â In "System Control" section, clarified Debug Access Port operation after Sleep modes.
â Clarified wording on Flash memory access errors.
â Added section on Flash interrupts.
â Clarified operation of SSI transmit FIFO.
â Made these changes to the Operating Characteristics chapter:
â Added storage temperature ratings to "Temperature Characteristics" table
â Added "ESD Absolute Maximum Ratings" table
â Made these changes to the Electrical Characteristics chapter:
â In "Flash Memory Characteristics" table, corrected Mass erase time
â Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
â In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
October 2009
6462
â Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
â Made these changes to the Electrical Characteristics chapter:
â Removed VSIH and VSIL parameters from Operating Conditions table.
â Added table showing actual PLL frequency depending on input crystal.
â Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS.
â Changed SSI set up and hold times to be expressed in system clocks, not ns.
July 2009
July 2009
5920
5902
Corrected ordering numbers.
â Clarified Power-on reset and RST pin operation; added new diagrams.
â Clarified explanation of nonvolatile register programming in Internal Memory chapter.
â Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
â Added description for Ethernet PHY power-saving modes.
â Corrected the reset values for bits 6 and 7 in the Ethernet MR24 register.
â Changed buffer type for WAKE pin to TTL and HIB pin to OD.
â In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR
(Internal voltage reference error) parameter.
â Additional minor data sheet clarifications and corrections.
April 2009
5367
â Added JTAG/SWD clarification (see âCommunication with JTAG/SWDâ on page 154).
â Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
â Added "GPIO Module DC Characteristics" table (see Table 17-4 on page 514).
â Additional minor data sheet clarifications and corrections.
22
June 18, 2012
Texas Instruments-Production Data
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