LM3S6100 Datasheet, PDF (500/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Signal Tables
Table 15-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
GNDA
B5
-
Power The ground reference for the analog circuits ( Analog Comparators,
etc.). These are separated from GND to minimize the electrical
noise contained on VDD from affecting the analog functions.
B6
GND
-
Power Ground reference for logic and I/O pins.
PB5
I/O
TTL
GPIO port B bit 5.
B7
C0o
O
TTL
Analog comparator 0 output.
PC2
I/O
TTL
GPIO port C bit 2.
B8
TDI
I
TTL
JTAG TDI.
PC1
I/O
TTL
GPIO port C bit 1.
B9
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I/O
TTL
JTAG TMS and SWDIO.
B10
CMOD1
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
B11
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
B12
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
C4
GND
-
Power Ground reference for logic and I/O pins.
C5
GND
-
Power Ground reference for logic and I/O pins.
VDDA
C6
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 513, regardless of system implementation.
VDDA
C7
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 513, regardless of system implementation.
C8
GNDPHY
-
Power GND of the Ethernet PHY.
C9
GNDPHY
-
Power GND of the Ethernet PHY.
C10
VCCPHY
-
Power VCC of the Ethernet PHY.
C11
PB2
I/O
TTL
GPIO port B bit 2.
C12
PB3
I/O
TTL
GPIO port B bit 3.
D1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
D10
VCCPHY
-
Power VCC of the Ethernet PHY.
D11
VCCPHY
-
Power VCC of the Ethernet PHY.
PB1
D12
CCP2
I/O
TTL
GPIO port B bit 1.
I/O
TTL
Capture/Compare/PWM 2.
500
June 18, 2012
Texas Instruments-Production Data