LM3S6100 Datasheet, PDF (3/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Stellaris^® LM3S6100 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 20
About This Document .................................................................................................................... 25
Audience .............................................................................................................................................. 25
About This Manual ................................................................................................................................ 25
Related Documents ............................................................................................................................... 25
Documentation Conventions .................................................................................................................. 26
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview .......................................................................................... 28
Product Features .......................................................................................................... 28
Target Applications ........................................................................................................ 34
High-Level Block Diagram ............................................................................................. 34
Functional Overview ...................................................................................................... 36
ARM Cortex™-M3 ......................................................................................................... 36
Motor Control Peripherals .............................................................................................. 37
Analog Peripherals ........................................................................................................ 37
Serial Communications Peripherals ................................................................................ 37
System Peripherals ....................................................................................................... 39
Memory Peripherals ...................................................................................................... 39
Additional Features ....................................................................................................... 40
Hardware Details .......................................................................................................... 40
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
2.5.3
The Cortex-M3 Processor ...................................................................................... 41
Block Diagram .............................................................................................................. 42
Overview ...................................................................................................................... 43
System-Level Interface .................................................................................................. 43
Integrated Configurable Debug ...................................................................................... 43
Trace Port Interface Unit (TPIU) ..................................................................................... 44
Cortex-M3 System Component Details ........................................................................... 44
Programming Model ...................................................................................................... 45
Processor Mode and Privilege Levels for Software Execution ........................................... 45
Stacks .......................................................................................................................... 45
Register Map ................................................................................................................ 46
Register Descriptions .................................................................................................... 47
Exceptions and Interrupts .............................................................................................. 60
Data Types ................................................................................................................... 60
Memory Model .............................................................................................................. 60
Memory Regions, Types and Attributes ........................................................................... 61
Memory System Ordering of Memory Accesses .............................................................. 62
Behavior of Memory Accesses ....................................................................................... 62
Software Ordering of Memory Accesses ......................................................................... 63
Bit-Banding ................................................................................................................... 64
Data Storage ................................................................................................................ 66
Synchronization Primitives ............................................................................................. 67
Exception Model ........................................................................................................... 68
Exception States ........................................................................................................... 69
Exception Types ............................................................................................................ 69
Exception Handlers ....................................................................................................... 71
June 18, 2012
3
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